vremu.vv
No synopsis available.
This instruction is defined by:
-
V, version >= 0
This instruction is included in the following profiles:
-
RVA22S64 (Optional)
-
RVA22U64 (Optional)
Decode Variables
Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> vs1 = $encoding[19:15];
Bits<5> vd = $encoding[11:7];
Execution
-
IDL
-
Sail
{
let SEW = get_sew();
let LMUL_pow = get_lmul_pow();
let num_elem = get_num_elem(LMUL_pow, SEW);
if illegal_normal(vd, vm) then { handle_illegal(); return RETIRE_FAIL };
let 'n = num_elem;
let 'm = SEW;
let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);
let vs1_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs1);
let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);
result : vector('n, dec, bits('m)) = undefined;
mask : vector('n, dec, bool) = undefined;
(result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);
foreach (i from 0 to (num_elem - 1)) {
if mask[i] then {
result[i] = match funct6 {
MVV_VAADDU => {
let result_add = zero_extend('m + 1, vs2_val[i]) + zero_extend('m + 1, vs1_val[i]);
let rounding_incr = get_fixed_rounding_incr(result_add, 1);
slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr)
},
MVV_VAADD => {
let result_add = sign_extend('m + 1, vs2_val[i]) + sign_extend('m + 1, vs1_val[i]);
let rounding_incr = get_fixed_rounding_incr(result_add, 1);
slice(result_add >> 1, 0, 'm) + zero_extend('m, rounding_incr)
},
MVV_VASUBU => {
let result_sub = zero_extend('m + 1, vs2_val[i]) - zero_extend('m + 1, vs1_val[i]);
let rounding_incr = get_fixed_rounding_incr(result_sub, 1);
slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr)
},
MVV_VASUB => {
let result_sub = sign_extend('m + 1, vs2_val[i]) - sign_extend('m + 1, vs1_val[i]);
let rounding_incr = get_fixed_rounding_incr(result_sub, 1);
slice(result_sub >> 1, 0, 'm) + zero_extend('m, rounding_incr)
},
MVV_VMUL => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), 0),
MVV_VMULH => get_slice_int(SEW, signed(vs2_val[i]) * signed(vs1_val[i]), SEW),
MVV_VMULHU => get_slice_int(SEW, unsigned(vs2_val[i]) * unsigned(vs1_val[i]), SEW),
MVV_VMULHSU => get_slice_int(SEW, signed(vs2_val[i]) * unsigned(vs1_val[i]), SEW),
MVV_VDIVU => {
let q : int = if unsigned(vs1_val[i]) == 0 then -1 else quot_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i]));
to_bits(SEW, q)
},
MVV_VDIV => {
let elem_max : int = 2 ^ (SEW - 1) - 1;
let elem_min : int = 0 - 2 ^ (SEW - 1);
let q : int = if signed(vs1_val[i]) == 0 then -1 else quot_round_zero(signed(vs2_val[i]), signed(vs1_val[i]));
/* check for signed overflow */
let q' : int = if q > elem_max then elem_min else q;
to_bits(SEW, q')
},
MVV_VREMU => {
let r : int = if unsigned(vs1_val[i]) == 0 then unsigned(vs2_val[i]) else rem_round_zero(unsigned(vs2_val[i]), unsigned(vs1_val[i]));
/* signed overflow case returns zero naturally as required due to -1 divisor */
to_bits(SEW, r)
},
MVV_VREM => {
let r : int = if signed(vs1_val[i]) == 0 then signed(vs2_val[i]) else rem_round_zero(signed(vs2_val[i]), signed(vs1_val[i]));
/* signed overflow case returns zero naturally as required due to -1 divisor */
to_bits(SEW, r)
}
}
}
};
write_vreg(num_elem, SEW, LMUL_pow, vd, result);
vstart = zeros();
RETIRE_SUCCESS
}