fsgnjx.s

Single-precision sign inject exclusive or

This instruction is defined by:

  • F, version >= 0

This instruction is included in the following profiles:

  • RVA20S64 (Mandatory)

  • RVA20U64 (Mandatory)

  • RVA22S64 (Mandatory)

  • RVA22U64 (Mandatory)

Encoding

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Assembly format

fsgnjx.s fd, fs1, fs2

Synopsis

This instruction must have data-independent timing when extension Zkt is enabled.

Writes fd with the xor of the sign bits of fs2 and fs1 and the exponent and mantissa of fs1.

Sign-injection instructions do not set floating-point exception flags, nor do they canonicalize NaNs.

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

Bits<5> fs2 = $encoding[24:20];
Bits<5> fs1 = $encoding[19:15];
Bits<5> fd = $encoding[11:7];

Execution

  • IDL

  • Sail

check_f_ok($encoding);
Bits<32> sp_value = {f[fs1][31] ^ f[fs2][31], f[fs1][30:0]};
if (implemented?(ExtensionName::D)) {
  f[fd] = nan_box<32, 64>(sp_value);
} else {
  f[fd] = sp_value;
}
mark_f_state_dirty();
{
  let rs1_val_S = F_or_X_S(rs1);
  let rs2_val_S = F_or_X_S(rs2);

  let (fflags, rd_val) : (bits_fflags, bool) =
      riscv_f32Le (rs1_val_S, rs2_val_S);

  accrue_fflags(fflags);
  X(rd) = zero_extend(bool_to_bits(rd_val));
  RETIRE_SUCCESS
}

Exceptions

This instruction may result in the following synchronous exceptions:

  • IllegalInstruction