ori

Or immediate

This instruction is defined by:

I, version >= 0

This instruction is included in the following profiles:

MockProfile 64-bit Unpriv (Mandatory)
MockProfile 64-bit S-mode (Mandatory)
RVA20U64 (Mandatory)
RVA22U64 (Mandatory)
RVI20U32 (Mandatory)
RVI20U64 (Mandatory)

Encoding

Assembly format

ori rd, rs1, imm

Synopsis

This instruction must have data-independent timing when extension Zkt is enabled.

Or an immediate to the value in rs1, and store the result in rd

Access

M	HS	U	VS	VU
Always	Always	Always	Always	Always

Always

Decode Variables

Bits<12> imm = $encoding[31:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];

Execution

IDL
Sail

if (implemented?(ExtensionName::Zicbop)) {
  if (rd == 0) {
    if (imm[4:0] == 0) {
      Bits<12> offset = {imm[11:5], rd};
      prefetch_instruction(offset);
    } else if (imm[4:0] == 1) {
      Bits<12> offset = {imm[11:5], rd};
      prefetch_read(offset);
    } else if (imm[4:0] == 3) {
      Bits<12> offset = {imm[11:5], rd};
      prefetch_write(offset);
    }
  }
}
X[rd] = X[rs1] | imm;

{
  let rs1_val = X(rs1);
  let immext : xlenbits = sign_extend(imm);
  let result : xlenbits = match op {
    RISCV_ADDI  => rs1_val + immext,
    RISCV_SLTI  => zero_extend(bool_to_bits(rs1_val <_s immext)),
    RISCV_SLTIU => zero_extend(bool_to_bits(rs1_val <_u immext)),
    RISCV_ANDI  => rs1_val & immext,
    RISCV_ORI   => rs1_val | immext,
    RISCV_XORI  => rs1_val ^ immext
  };
  X(rd) = result;
  RETIRE_SUCCESS
}