mcause

Machine Cause

Reports the cause of the latest exception.

Attributes

Defining Extension

  • Sm, version >= 0

CSR Address

0x342

Length

32-bit

64-bit

Privilege Mode

M

Format

This CSR format changes dynamically.

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Field Summary

Name Location Type Reset Value

INT

63

RW-RH

0

CODE

62:0

RW-RH

0

Fields

INT

Location

63

Description

Written by hardware when a trap is taken into M-mode.

When set, the last exception was caused by an asynchronous Interrupt.

mcause.INT is writeable.

[when,"TRAP_ON_ILLEGAL_WLRL == true"]
If mcause is written with an undefined cause (combination of mcause.INT and mcause.CODE), an Illegal Instruction exception occurs.

[when,"TRAP_ON_ILLEGAL_WLRL == false"]
If mcause is written with an undefined cause (combination of mcause.INT and mcause.CODE), neither mcause.INT nor mcause.CODE are modified.

Type

RW-RH

Reset value

0

CODE

Location

62:0

Description

Written by hardware when a trap is taken into M-mode.

Holds the interrupt or exception code for the last taken trap.

mcause.CODE is writeable.

[when,"TRAP_ON_ILLEGAL_WLRL == true"]
If mcause is written with an undefined cause (combination of mcause.INT and mcause.CODE), an Illegal Instruction exception occurs.

[when,"TRAP_ON_ILLEGAL_WLRL == false"]
If mcause is written with an undefined cause (combination of mcause.INT and mcause.CODE), neither mcause.INT nor mcause.CODE are modified.

Valid interrupt codes are:
[separator="!"]
!===
! 1 ! Supervisor software interrupt
! 2 ! Virtual supervisor software interrupt
! 3 ! Machine software interrupt
! 5 ! Supervisor timer interrupt
! 6 ! Virtual supervisor timer interrupt
! 7 ! Machine timer interrupt
! 9 ! Supervisor external interrupt
! 10 ! Virtual supervisor external interrupt
! 11 ! Machine external interrupt
! 12 ! Supervisor guest external interrupt
!===

Valid exception codes are:
[separator="!"]
!===
! 0 ! Instruction address misaligned
! 1 ! Instruction access fault
! 2 ! Illegal instruction
! 3 ! Breakpoint
! 4 ! Load address misaligned
! 5 ! Load access fault
! 6 ! Store/AMO address misaligned
! 7 ! Store/AMO access fault
! 8 ! Environment call from <%- if ext?(:H) -%>V<%- end -%>U-mode
! 9 ! Environment call from <%- if ext?(:H) -%>H<%- end -%>S-mode
! 10 ! Environment call from VS-mode
! 11 ! Environment call from M-mode
! 12 ! Instruction page fault
! 13 ! Load page fault
! 15 ! Store/AMO page fault
! 18 ! Software Check
! 20 ! Instruction guest page fault
! 21 ! Load guest page fault
! 22 ! Virtual instruction
! 23 ! Store/AMO guest page fault
!===

Type

RW-RH

Reset value

0

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

INT = # the write only holds if the INT/CODE combination is valid
if (csr_value.INT == 1) {
  if (valid_interrupt_code?(csr_value.CODE)) {
    return 1;
  }
  return ILLEGAL_WLRL;
} else {
  if (valid_exception_code?(csr_value.CODE)) {
    return 1;
  }
  return ILLEGAL_WLRL;
}

CODE = # the write only holds if the INT/CODE combination is valid
if (csr_value.INT == 1) {
  if (valid_interrupt_code?(csr_value.CODE)) {
    return csr_value.CODE;
  }
  return ILLEGAL_WLRL;
} else {
  if (valid_exception_code?(csr_value.CODE)) {
    return csr_value.CODE;
  }
  return ILLEGAL_WLRL;
}