sraiw

Shift right arithmetic immediate word

This instruction is defined by:

I, version >= 0

This instruction is included in the following profiles:

RVA20S64 (Mandatory)
RVA20U64 (Mandatory)
RVA22S64 (Mandatory)
RVA22U64 (Mandatory)

Encoding

Assembly format

sraiw rd, rs1, shamt

Synopsis

This instruction must have data-independent timing when extension Zkt is enabled.

Arithmetic shift (the original sign bit is copied into the vacated upper bits) the 32-bit value in rs1 right by shamt, and store the sign-extended result in rd.

Access

M	HS	U	VS	VU
Always	Always	Always	Always	Always

Always

Decode Variables

Bits<5> shamt = $encoding[24:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];

Execution

IDL
Sail

XReg operand = sext(X[rs1], 31);
X[rd] = sext(operand >>> shamt, 31);

{
  let rs1_val = (X(rs1))[31..0];
  let result : bits(32) = match op {
    RISCV_SLLIW => rs1_val << shamt,
    RISCV_SRLIW => rs1_val >> shamt,
    RISCV_SRAIW => shift_right_arith32(rs1_val, shamt)
  };
  X(rd) = sign_extend(result);
  RETIRE_SUCCESS
}