stvec

Supervisor Trap Vector

Controls where traps jump.

Attributes

Defining Extension	S, version >= 0
CSR Address	0x105
Length	64-bit
Privilege Mode	S

Defining Extension

S, version >= 0

CSR Address

0x105

Length

64-bit

Privilege Mode

Format

Figure 1. stvec format

Field Summary

Name Location Type Reset Value

Name	Location	Type	Reset Value
`BASE`	63:2	RW-R	UNDEFINED_LEGAL
`MODE`	1:0	RW-R	0

BASE

63:2

RW-R

UNDEFINED_LEGAL

MODE

1:0

RW-R

Fields

`BASE`

Location: 63:2
Description: Bit 63:0 of the virtual address of the exception vector for any trap taken into S-mode.

If the base address is written with a non-cannonical address (i.e., bits 63:39 do not match bit 38),
the write should be ignored.
Type: RW-R
Reset value: UNDEFINED_LEGAL

`MODE`

Location: 1:0
Description: Vectoring mode for asynchronous interrupts.

0 - Direct, 1 - Vectored

When Direct, all synchronous exceptions and asynchronous interrupts jump to (stvec.BASE << 2).

When Vectored, asynchronous interrupts jump to (stvec.BASE << 2 + scause*4) while synchronous exceptions continue to jump to (stvec.BASE << 2).
Type: RW-R
Reset value: 0

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

BASE = # Base spec says that BASE must be 4-byte aligned, which will always be the case
# implementations may put further constraints on BASE when MODE != Direct
# If that is the case, stvec should have an override for the implementation
return csr_value.BASE;

MODE = if (STVEC_MODE_DIRECT && csr_value.MODE == 0) {
  return 0;
} else if (STVEC_MODE_VECTORED && csr_value.MODE == 1) {
  return 1;
} else {
  return UNDEFINED_LEGAL_DETERMINISTIC;
}