The counter-enable mcounteren register is a 32-bit register that controls the availability
of the hardware performance-monitoring counters to
the next-lower privileged mode
.
The settings in this register only control accessibility. The act of reading or writing this
register does not affect the underlying counters, which continue to increment even when not
accessible.
When the CY, TM, IR, or HPMn bit in the mcounteren register is clear, attempts to read the
cycle, time, instret, or hpmcountern register while executing in
S-mode or U-mode
will cause an IllegalInstruction exception. When one of these bits is set, access to the
corresponding register is permitted in
the next implemented privilege mode (S-mode if implemented, otherwise U-mode).
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The counter-enable bits support two common use cases with minimal hardware.
For harts that do not need high-performance timers and counters, machine-mode software can
trap accesses and implement all features in software. For harts that need high-performance
timers and counters but are not concerned with obfuscating the underlying hardware counters,
the counters can be directly exposed to lower privilege modes.
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The cycle, instret, and hpmcountern CSRs are read-only shadows of mcycle, minstret,
and mhpmcounter n, respectively. The time CSR is a read-only shadow of the memory-mapped
mtime register.
Analogously, on RV32I the cycleh, instreth and hpmcounternh CSRs are
read-only shadows of mcycleh, minstreth and mhpmcounternh, respectively.
On RV32I the timeh CSR is a read-only shadow of the upper 32 bits of the memory-mapped mtime
register, while time shadows only the lower 32 bits of mtime.
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Implementations can convert reads of the time and timeh CSRs into loads to the
memory-mapped mtime register, or emulate this functionality on behalf of less-privileged
modes in M-mode software.
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In harts with U-mode, the mcounteren CSR must be implemented, but all fields are WARL and may
be read-only zero, indicating reads to the corresponding counter will cause an
IllegalInstruction exception when executing in a less-privileged mode.
In harts without U-mode, the mcounteren register should not exist.