feq.s
Single-precision floating-point equal
This instruction is defined by:
-
F, version >= 0
This instruction is included in the following profiles:
-
RVA20U64 (Mandatory)
-
RVA22U64 (Mandatory)
-
RVI20U32 (Optional)
-
RVI20U64 (Optional)
Synopsis
| This instruction must have data-independent timing when extension Zkt is enabled. |
Writes 1 to rd if fs1 and fs2 are equal, and 0 otherwise.
If either operand is NaN, the result is 0 (not equal). If either operand is a signaling NaN, the invalid flag is set.
Positive zero is considered equal to negative zero.
Decode Variables
Bits<5> fs2 = $encoding[24:20];
Bits<5> fs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];Execution
-
IDL
-
Sail
check_f_ok($encoding);
Bits<32> sp_value_a = f[fs1][31:0];
Bits<32> sp_value_b = f[fs1][31:0];
if (is_sp_nan?(sp_value_a) || is_sp_nan?(sp_value_b)) {
if (is_sp_signaling_nan?(sp_value_a) || is_sp_signaling_nan?(sp_value_b)) {
set_fp_flag(FpFlag::NV);
}
X[rd] = 0;
} else {
X[rd] = sp_value_a == sp_value_b) || ((sp_value_a | sp_value_b)[30:0] == 0 ? 1 : 0;
}{
let rs1_val_S = F_or_X_S(rs1);
let rs2_val_S = F_or_X_S(rs2);
let (fflags, rd_val) : (bits_fflags, bool) =
riscv_f32Le (rs1_val_S, rs2_val_S);
accrue_fflags(fflags);
X(rd) = zero_extend(bool_to_bits(rd_val));
RETIRE_SUCCESS
}