RV32/64G Instruction Set Listings

One goal of the RISC-V project is that it be used as a stable software development target. For this purpose, we define a combination of a base ISA (RV32I or RV64I) plus selected standard extensions (IMAFD, Zicsr, Zifencei) as a "general-purpose" ISA, and we use the abbreviation G for the IMAFDZicsr_Zifencei combination of instruction-set extensions. This chapter presents opcode maps and instruction-set listings for RV32G and RV64G.

Table 1. RISC-V base opcode map, inst[1:0]=11

inst[4:2]

000

001

010

011

100

101

110

111 (>32b)

inst[6:5]

00

LOAD

LOAD-FP

custom-0

MISC-MEM

OP-IMM

AUIPC

OP-IMM-32

48b

01

STORE

STORE-FP

custom-1

AMO

OP

LUI

OP-32

64b

10

MADD

MSUB

NMSUB

NMADD

OP-FP

OP-V

custom-2/rv128

48b

11

BRANCH

JALR

reserved

JAL

SYSTEM

OP-VE

custom-3/rv128

≥80b

RISC-V base opcode map, inst[1:0]=11 shows a map of the major opcodes for RVG. Major opcodes with 3 or more lower bits set are reserved for instruction lengths greater than 32 bits. Opcodes marked as reserved should be avoided for custom instruction-set extensions as they might be used by future standard extensions. Major opcodes marked as custom-0 and custom-1 will be avoided by future standard extensions and are recommended for use by custom instruction-set extensions within the base 32-bit instruction format. The opcodes marked custom-2/rv128 and custom-3/rv128 are reserved for future use by RV128, but will otherwise be avoided for standard extensions and so can also be used for custom instruction-set extensions in RV32 and RV64.

We believe RV32G and RV64G provide simple but complete instruction sets for a broad range of general-purpose computing. The optional compressed instruction set described in [compressed] can be added (forming RV32GC and RV64GC) to improve performance, code size, and energy efficiency, though with some additional hardware complexity.

As we move beyond IMAFDC into further instruction-set extensions, the added instructions tend to be more domain-specific and only provide benefits to a restricted class of applications, e.g., for multimedia or security. Unlike most commercial ISAs, the RISC-V ISA design clearly separates the base ISA and broadly applicable standard extensions from these more specialized additions. [extending] has a more extensive discussion of ways to add extensions to the RISC-V ISA.

31

27

26

25

24

20

19

15

14

12

11

7

6

0

funct7

rs2

rs1

funct3

rd

opcode

R-type

imm[11:0]

rs1

funct3

rd

opcode

I-type

imm[11:5]

rs2

rs1

funct3

imm[4:0]

opcode

S-type

imm[12|10:5]

rs2

rs1

funct3

imm[4:1|11]

opcode

B-type

imm[31:12]

rd

opcode

U-type

imm[20|10:1|11|19:12]

rd

opcode

J-type

RV32I Base Instruction Set

imm[31:12]

rd

0110111

LUI

imm[31:12]

rd

0010111

AUIPC

imm[20|10:1|11|19:12]

rd

1101111

JAL

imm[11:0]

rs1

000

rd

1100111

JALR

imm[12|10:5]

rs2

rs1

000

imm[4:1|11]

1100011

BEQ

imm[12|10:5]

rs2

rs1

001

imm[4:1|11]

1100011

BNE

imm[12|10:5]

rs2

rs1

100

imm[4:1|11]

1100011

BLT

imm[12|10:5]

rs2

rs1

101

imm[4:1|11]

1100011

BGE

imm[12|10:5]

rs2

rs1

110

imm[4:1|11]

1100011

BLTU

imm[12|10:5]

rs2

rs1

111

imm[4:1|11]

1100011

BGEU

imm[11:0]

rs1

000

rd

0000011

LB

imm[11:0]

rs1

001

rd

0000011

LH

imm[11:0]

rs1

010

rd

0000011

LW

imm[11:0]

rs1

100

rd

0000011

LBU

imm[11:0]

rs1

101

rd

0000011

LHU

imm[11:5]

rs2

rs1

000

imm[4:0]

0100011

SB

imm[11:5]

rs2

rs1

001

imm[4:0]

0100011

SH

imm[11:5]

rs2

rs1

010

imm[4:0]

0100011

SW

imm[11:0]

rs1

000

rd

0010011

ADDI

imm[11:0]

rs1

010

rd

0010011

SLTI

imm[11:0]

rs1

011

rd

0010011

SLTIU

imm[11:0]

rs1

100

rd

0010011

XORI

imm[11:0]

rs1

110

rd

0010011

ORI

imm[11:0]

rs1

111

rd

0010011

ANDI

0000000

shamt

rs1

001

rd

0010011

SLLI

0000000

shamt

rs1

101

rd

0010011

SRLI

0100000

shamt

rs1

101

rd

0010011

SRAI

0000000

rs2

rs1

000

rd

0110011

ADD

0100000

rs2

rs1

000

rd

0110011

SUB

0000000

rs2

rs1

001

rd

0110011

SLL

0000000

rs2

rs1

010

rd

0110011

SLT

0000000

rs2

rs1

011

rd

0110011

SLTU

0000000

rs2

rs1

100

rd

0110011

XOR

0000000

rs2

rs1

101

rd

0110011

SRL

0100000

rs2

rs1

101

rd

0110011

SRA

0000000

rs2

rs1

110

rd

0110011

OR

0000000

rs2

rs1

111

rd

0110011

AND

fm

pred

succ

rs1

000

rd

0001111

FENCE

1000

0011

0011

00000

000

00000

0001111

FENCE.TSO

0000

0001

0000

00000

000

00000

0001111

PAUSE

000000000000

00000

000

00000

1110011

ECALL

000000000001

00000

000

00000

1110011

EBREAK

31

27

26

25

24

20

19

15

14

12

11

7

6

0

funct7

rs2

rs1

funct3

rd

opcode

R-type

imm[11:0]

rs1

funct3

rd

opcode

I-type

imm[11:5]

rs2

rs1

funct3

imm[4:0]

opcode

S-type

RV64I Base Instruction Set (in addition to RV32I)

imm[11:0]

rs1

110

rd

0000011

LWU

imm[11:0]

rs1

011

rd

0000011

LD

imm[11:5]

rs2

rs1

011

imm[4:0]

0100011

SD

000000

shamt

rs1

001

rd

0010011

SLLI

000000

shamt

rs1

101

rd

0010011

SRLI

010000

shamt

rs1

101

rd

0010011

SRAI

imm[11:0]

rs1

000

rd

0011011

ADDIW

0000000

shamt

rs1

001

rd

0011011

SLLIW

0000000

shamt

rs1

101

rd

0011011

SRLIW

0100000

shamt

rs1

101

rd

0011011

SRAIW

0000000

rs2

rs1

000

rd

0111011

ADDW

0100000

rs2

rs1

000

rd

0111011

SUBW

0000000

rs2

rs1

001

rd

0111011

SLLW

0000000

rs2

rs1

101

rd

0111011

SRLW

0100000

rs2

rs1

101

rd

0111011

SRAW

RV32/RV64 Zifencei Standard Extension

imm[11:0]

rs1

001

rd

0001111

FENCE.I

RV32/RV64 Zicsr Standard Extension

csr

rs1

001

rd

1110011

CSRRW

csr

rs1

010

rd

1110011

CSRRS

csr

rs1

011

rd

1110011

CSRRC

csr

uimm

101

rd

1110011

CSRRWI

csr

uimm

110

rd

1110011

CSRRSI

csr

uimm

111

rd

1110011

CSRRCI

RV32M Standard Extension

0000001

rs2

rs1

000

rd

0110011

MUL

0000001

rs2

rs1

001

rd

0110011

MULH

0000001

rs2

rs1

010

rd

0110011

MULHSU

0000001

rs2

rs1

011

rd

0110011

MULHU

0000001

rs2

rs1

100

rd

0110011

DIV

0000001

rs2

rs1

101

rd

0110011

DIVU

0000001

rs2

rs1

110

rd

0110011

REM

0000001

rs2

rs1

111

rd

0110011

REMU

RV64M Standard Extension (in addition to RV32M)

0000001

rs2

rs1

000

rd

0111011

MULW

0000001

rs2

rs1

100

rd

0111011

DIVW

0000001

rs2

rs1

101

rd

0111011

DIVUW

0000001

rs2

rs1

110

rd

0111011

REMW

0000001

rs2

rs1

111

rd

0111011

REMUW

31

27

26

25

24

20

19

15

14

12

11

7

6

0

funct7

rs2

rs1

funct3

rd

opcode

R-type

RV32A Standard Extension

00010

aq

rl

00000

rs1

010

rd

0101111

LR.W

00011

aq

rl

rs2

rs1

010

rd

0101111

SC.W

00001

aq

rl

rs2

rs1

010

rd

0101111

AMOSWAP.W

00000

aq

rl

rs2

rs1

010

rd

0101111

AMOADD.W

00100

aq

rl

rs2

rs1

010

rd

0101111

AMOXOR.W

01100

aq

rl

rs2

rs1

010

rd

0101111

AMOAND.W

01000

aq

rl

rs2

rs1

010

rd

0101111

AMOOR.W

10000

aq

rl

rs2

rs1

010

rd

0101111

AMOMIN.W

10100

aq

rl

rs2

rs1

010

rd

0101111

AMOMAX.W

11000

aq

rl

rs2

rs1

010

rd

0101111

AMOMINU.W

11100

aq

rl

rs2

rs1

010

rd

0101111

AMOMAXU.W

RV64A Standard Extension (in addition to RV32A)

00010

aq

rl

00000

rs1

011

rd

0101111

LR.D

00011

aq

rl

rs2

rs1

011

rd

0101111

SC.D

00001

aq

rl

rs2

rs1

011

rd

0101111

AMOSWAP.D

00000

aq

rl

rs2

rs1

011

rd

0101111

AMOADD.D

00100

aq

rl

rs2

rs1

011

rd

0101111

AMOXOR.D

01100

aq

rl

rs2

rs1

011

rd

0101111

AMOAND.D

01000

aq

rl

rs2

rs1

011

rd

0101111

AMOOR.D

10000

aq

rl

rs2

rs1

011

rd

0101111

AMOMIN.D

10100

aq

rl

rs2

rs1

011

rd

0101111

AMOMAX.D

11000

aq

rl

rs2

rs1

011

rd

0101111

AMOMINU.D

11100

aq

rl

rs2

rs1

011

rd

0101111

AMOMAXU.D

31

27

26

25

24

20

19

15

14

12

11

7

6

0

funct7

rs2

rs1

funct3

rd

opcode

R-type

rs3

funct2

rs2

rs1

funct3

rd

opcode

R4-type

imm[11:0]

rs1

funct3

rd

opcode

I-type

imm[11:5]

rs2

rs1

funct3

imm[4:0]

opcode

S-type

RV32F Standard Extension

imm[11:0]

rs1

010

rd

0000111

FLW

imm[11:5]

rs2

rs1

010

imm[4:0]

0100111

FSW

rs3

00

rs2

rs1

rm

rd

1000011

FMADD.S

rs3

00

rs2

rs1

rm

rd

1000111

FMSUB.S

rs3

00

rs2

rs1

rm

rd

1001011

FNMSUB.S

rs3

00

rs2

rs1

rm

rd

1001111

FNMADD.S

0000000

rs2

rs1

rm

rd

1010011

FADD.S

0000100

rs2

rs1

rm

rd

1010011

FSUB.S

0001000

rs2

rs1

rm

rd

1010011

FMUL.S

0001100

rs2

rs1

rm

rd

1010011

FDIV.S

0101100

00000

rs1

rm

rd

1010011

FSQRT.S

0010000

rs2

rs1

000

rd

1010011

FSGNJ.S

0010000

rs2

rs1

001

rd

1010011

FSGNJN.S

0010000

rs2

rs1

010

rd

1010011

FSGNJX.S

0010100

rs2

rs1

000

rd

1010011

FMIN.S

0010100

rs2

rs1

001

rd

1010011

FMAX.S

1100000

00000

rs1

rm

rd

1010011

FCVT.W.S

1100000

00001

rs1

rm

rd

1010011

FCVT.WU.S

1110000

00000

rs1

000

rd

1010011

FMV.X.W

1010000

rs2

rs1

010

rd

1010011

FEQ.S

1010000

rs2

rs1

001

rd

1010011

FLT.S

1010000

rs2

rs1

000

rd

1010011

FLE.S

1110000

00000

rs1

001

rd

1010011

FCLASS.S

1101000

00000

rs1

rm

rd

1010011

FCVT.S.W

1101000

00001

rs1

rm

rd

1010011

FCVT.S.WU

1111000

00000

rs1

000

rd

1010011

FMV.W.X

RV64F Standard Extension (in addition to RV32F)

1100000

00010

rs1

rm

rd

1010011

FCVT.L.S

1100000

00011

rs1

rm

rd

1010011

FCVT.LU.S

1101000

00010

rs1

rm

rd

1010011

FCVT.S.L

1101000

00011

rs1

rm

rd

1010011

FCVT.S.LU

31

27

26

25

24

20

19

15

14

12

11

7

6

0

funct7

rs2

rs1

funct3

rd

opcode

R-type

rs3

funct2

rs2

rs1

funct3

rd

opcode

R4-type

imm[11:0]

rs1

funct3

rd

opcode

I-type

imm[11:5]

rs2

rs1

funct3

imm[4:0]

opcode

S-type

RV32D Standard Extension

imm[11:0]

rs1

011

rd

0000111

FLD

imm[11:5]

rs2

rs1

011

imm[4:0]

0100111

FSD

rs3

01

rs2

rs1

rm

rd

1000011

FMADD.D

rs3

01

rs2

rs1

rm

rd

1000111

FMSUB.D

rs3

01

rs2

rs1

rm

rd

1001011

FNMSUB.D

rs3

01

rs2

rs1

rm

rd

1001111

FNMADD.D

0000001

rs2

rs1

rm

rd

1010011

FADD.D

0000101

rs2

rs1

rm

rd

1010011

FSUB.D

0001001

rs2

rs1

rm

rd

1010011

FMUL.D

0001101

rs2

rs1

rm

rd

1010011

FDIV.D

0101101

00000

rs1

rm

rd

1010011

FSQRT.D

0010001

rs2

rs1

000

rd

1010011

FSGNJ.D

0010001

rs2

rs1

001

rd

1010011

FSGNJN.D

0010001

rs2

rs1

010

rd

1010011

FSGNJX.D

0010101

rs2

rs1

000

rd

1010011

FMIN.D

0010101

rs2

rs1

001

rd

1010011

FMAX.D

0100000

00001

rs1

rm

rd

1010011

FCVT.S.D

0100001

00000

rs1

rm

rd

1010011

FCVT.D.S

1010001

rs2

rs1

010

rd

1010011

FEQ.D

1010001

rs2

rs1

001

rd

1010011

FLT.D

1010001

rs2

rs1

000

rd

1010011

FLE.D

1110001

00000

rs1

001

rd

1010011

FCLASS.D

1100001

00000

rs1

rm

rd

1010011

FCVT.W.D

1100001

00001

rs1

rm

rd

1010011

FCVT.WU.D

1101001

00000

rs1

rm

rd

1010011

FCVT.D.W

1101001

00001

rs1

rm

rd

1010011

FCVT.D.WU

RV64D Standard Extension (in addition to RV32D)

1100001

00010

rs1

rm

rd

1010011

FCVT.L.D

1100001

00011

rs1

rm

rd

1010011

FCVT.LU.D

1110001

00000

rs1

000

rd

1010011

FMV.X.D

1101001

00010

rs1

rm

rd

1010011

FCVT.D.L

1101001

00011

rs1

rm

rd

1010011

FCVT.D.LU

1111001

00000

rs1

000

rd

1010011

FMV.D.X

31

27

26

25

24

20

19

15

14

12

11

7

6

0

funct7

rs2

rs1

funct3

rd

opcode

R-type

rs3

funct2

rs2

rs1

funct3

rd

opcode

R4-type

imm[11:0]

rs1

funct3

rd

opcode

I-type

imm[11:5]

rs2

rs1

funct3

imm[4:0]

opcode

S-type

31

27

26

25

24

20

19

15

14

12

11

7

6

0

funct7

rs2

rs1

funct3

rd

opcode

R-type

rs3

funct2

rs2

rs1

funct3

rd

opcode

R4-type

imm[11:0]

rs1

funct3

rd

opcode

I-type

imm[11:5]

rs2

rs1

funct3

imm[4:0]

opcode

S-type

RV32Q Standard Extension

imm[11:0]

rs1

100

rd

0000111

FLQ

imm[11:5]

rs2

rs1

100

imm[4:0]

0100111

FSQ

rs3

11

rs2

rs1

rm

rd

1000011

FMADD.Q

rs3

11

rs2

rs1

rm

rd

1000111

FMSUB.Q

rs3

11

rs2

rs1

rm

rd

1001011

FNMSUB.Q

rs3

11

rs2

rs1

rm

rd

1001111

FNMADD.Q

0000011

rs2

rs1

rm

rd

1010011

FADD.Q

0000111

rs2

rs1

rm

rd

1010011

FSUB.Q

0001011

rs2

rs1

rm

rd

1010011

FMUL.Q

0001111

rs2

rs1

rm

rd

1010011

FDIV.Q

0101111

00000

rs1

rm

rd

1010011

FSQRT.Q

0010011

rs2

rs1

000

rd

1010011

FSGNJ.Q

0010011

rs2

rs1

001

rd

1010011

FSGNJN.Q

0010011

rs2

rs1

010

rd

1010011

FSGNJX.Q

0010111

rs2

rs1

000

rd

1010011

FMIN.Q

0010111

rs2

rs1

001

rd

1010011

FMAX.Q

0100000

00011

rs1

rm

rd

1010011

FCVT.S.Q

0100011

00000

rs1

rm

rd

1010011

FCVT.Q.S

0100001

00011

rs1

rm

rd

1010011

FCVT.D.Q

0100011

00001

rs1

rm

rd

1010011

FCVT.Q.D

1010011

rs2

rs1

010

rd

1010011

FEQ.Q

1010011

rs2

rs1

001

rd

1010011

FLT.Q

1010011

rs2

rs1

000

rd

1010011

FLE.Q

1110011

00000

rs1

001

rd

1010011

FCLASS.Q

1100011

00000

rs1

rm

rd

1010011

FCVT.W.Q

1100011

00001

rs1

rm

rd

1010011

FCVT.WU.Q

1101011

00000

rs1

rm

rd

1010011

FCVT.Q.W

1101011

00001

rs1

rm

rd

1010011

FCVT.Q.WU

RV64Q Standard Extension (in addition to RV32Q)

1100011

00010

rs1

rm

rd

1010011

FCVT.L.Q

1100011

00011

rs1

rm

rd

1010011

FCVT.LU.Q

1101011

00010

rs1

rm

rd

1010011

FCVT.Q.L

1101011

00011

rs1

rm

rd

1010011

FCVT.Q.LU

31

27

26

25

24

20

19

15

14

12

11

7

6

0

funct7

rs2

rs1

funct3

rd

opcode

R-type

rs3

funct2

rs2

rs1

funct3

rd

opcode

R4-type

imm[11:0]

rs1

funct3

rd

opcode

I-type

imm[11:5]

rs2

rs1

funct3

imm[4:0]

opcode

S-type

RV32Zfh Standard Extension

imm[11:0]

rs1

001

rd

0000111

FLH

imm[11:5]

rs2

rs1

001

imm[4:0]

0100111

FSH

rs3

10

rs2

rs1

rm

rd

1000011

FMADD.H

rs3

10

rs2

rs1

rm

rd

1000111

FMSUB.H

rs3

10

rs2

rs1

rm

rd

1001011

FNMSUB.H

rs3

10

rs2

rs1

rm

rd

1001111

FNMADD.H

0000010

rs2

rs1

rm

rd

1010011

FADD.H

0000110

rs2

rs1

rm

rd

1010011

FSUB.H

0001010

rs2

rs1

rm

rd

1010011

FMUL.H

0001110

rs2

rs1

rm

rd

1010011

FDIV.H

0101110

00000

rs1

rm

rd

1010011

FSQRT.H

0010010

rs2

rs1

000

rd

1010011

FSGNJ.H

0010010

rs2

rs1

001

rd

1010011

FSGNJN.H

0010010

rs2

rs1

010

rd

1010011

FSGNJX.H

0010110

rs2

rs1

000

rd

1010011

FMIN.H

0010110

rs2

rs1

001

rd

1010011

FMAX.H

0100000

00010

rs1

rm

rd

1010011

FCVT.S.H

0100010

00000

rs1

rm

rd

1010011

FCVT.H.S

0100001

00010

rs1

rm

rd

1010011

FCVT.D.H

0100010

00001

rs1

rm

rd

1010011

FCVT.H.D

0100011

00010

rs1

rm

rd

1010011

FCVT.Q.H

0100010

00011

rs1

rm

rd

1010011

FCVT.H.Q

1010010

rs2

rs1

010

rd

1010011

FEQ.H

1010010

rs2

rs1

001

rd

1010011

FLT.H

1010010

rs2

rs1

000

rd

1010011

FLE.H

1110010

00000

rs1

001

rd

1010011

FCLASS.H

1100010

00000

rs1

rm

rd

1010011

FCVT.W.H

1100010

00001

rs1

rm

rd

1010011

FCVT.WU.H

1110010

00000

rs1

000

rd

1010011

FMV.X.H

1101010

00000

rs1

rm

rd

1010011

FCVT.H.W

1101010

00001

rs1

rm

rd

1010011

FCVT.H.WU

1111010

00000

rs1

000

rd

1010011

FMV.H.X

RV64Zfh Standard Extension (in addition to RV32Zfh)

1100010

00010

rs1

rm

rd

1010011

FCVT.L.H

1100010

00011

rs1

rm

rd

1010011

FCVT.LU.H

1101010

00010

rs1

rm

rd

1010011

FCVT.H.L

1101010

00011

rs1

rm

rd

1010011

FCVT.H.LU

Zawrs Standard Extension

000000001101

00000

000

00000

1110011

WRS.NTO

000000011101

00000

000

00000

1110011

WRS.STO

RISC-V control and status register (CSR) address map. lists the CSRs that have currently been allocated CSR addresses. The timers, counters, and floating-point CSRs are the only CSRs defined in this specification.

Table 2. RISC-V control and status register (CSR) address map.
Number Privilege Name Description

Floating-Point Control and Status Registers

0x001

Read write

fflags

Floating-Point Accrued Exceptions.

0x002

Read write

frm

Floating-Point Dynamic Rounding Mode.

0x003

Read write

fcsr

Floating-Point Control and Status Register (frm + fflags).

Counters and Timers

0xC00

Read-only

cycle

Cycle counter for RDCYCLE instruction.

0xC01

Read-only

time

Timer for RDTIME instruction.

0xC02

Read-only

instret

Instructions-retired counter for RDINSTRET instruction.

0xC80

Read-only

cycleh

Upper 32 bits of cycle, RV32I only.

0xC81

Read-only

timeh

Upper 32 bits of time, RV32I only.

0xC82

Read-only

instreth

Upper 32 bits of instret, RV32I only.