mepc

Machine Exception Program Counter

Written with the PC of an instruction on an exception or interrupt taken in M-mode.

Also controls where the hart jumps on an exception return from M-mode.

Attributes

Defining Extension

CSR Address

0x341

Length

32-bit

64-bit

Privilege Mode

This CSR format changes dynamically.

Name Location Type Reset Value

Name	Location	Type	Reset Value
`PC`	63:0	RW-RH	0

63:0

RW-RH

Location: 63:0
Description: When a trap is taken into M-mode, mepc.PC is written with the virtual address of the
instruction that was interrupted or that encountered the exception.
Otherwise, mepc.PC is never written by the implementation, though it may be explicitly written
by software.

On an exception retun from M-mode (from the MRET instruction),
control transfers to the virtual address read out of mepc.PC.

[when,"ext?(:C)"]
Because PCs are always halfword-aligned, bit 0 of mepc.PC is always
read-only 0.

[when,"!ext?(:C)"]
Because PCs are always word-aligned, bits 1:0 of mepc.PC are always
read-only 0.

[when,"ext?(:C) && MUTABLE_MISA_C == true"]
When misa.C is clear, bit 1 is masked to zero. Writes to bit 1 are still captured, and
may be visible on the next read with misa.C is set.
Type: RW-RH
Reset value: 0

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

PC = return csr_value.PC & ~64'b1;

This CSR may return a value that is different from what is stored in hardware.

if (implemented?(ExtensionName::C) && CSR[misa].C == 1'b1) {
  return CSR[mepc].PC & ~64'b1;
} else {
  return CSR[mepc].PC;
}