vfwcvt.rtz.x.f.v

No synopsis available.

This instruction is defined by:

  • V, version >= 0

This instruction is included in the following profiles:

  • RVA22U64 (Optional)

Encoding

svg

Assembly format

vfwcvt.rtz.x.f.v vm, vs2, vd

Synopsis

No description available.

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> vd = $encoding[11:7];

Execution

  • IDL

  • Sail

{
  let rm_3b    = fcsr.FRM();
  let SEW      = get_sew();
  let LMUL_pow = get_lmul_pow();
  let num_elem = get_num_elem(LMUL_pow, SEW);
  let SEW_widen      = SEW * 2;
  let LMUL_pow_widen = LMUL_pow + 1;

  if  illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) |
      not(valid_reg_overlap(vs2, vd, LMUL_pow, LMUL_pow_widen))
  then { handle_illegal(); return RETIRE_FAIL };
  assert(SEW >= 8 & SEW_widen <= 64);

  let 'n = num_elem;
  let 'm = SEW;
  let 'o = SEW_widen;

  let vm_val  : vector('n, dec, bool)     = read_vmask(num_elem, vm, 0b00000);
  let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
  let vd_val  : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd);
  result      : vector('n, dec, bits('o)) = undefined;
  mask        : vector('n, dec, bool)     = undefined;

  (result, mask) = init_masked_result(num_elem, SEW_widen, LMUL_pow_widen, vd_val, vm_val);

  foreach (i from 0 to (num_elem - 1)) {
    if mask[i] then {
      result[i] = match vfwunary0 {
        FWV_CVT_XU_F     => {
                              let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {
                                8  => { handle_illegal(); return RETIRE_FAIL },
                                16 => riscv_f16ToUi32(rm_3b, vs2_val[i]),
                                32 => riscv_f32ToUi64(rm_3b, vs2_val[i])
                              };
                              accrue_fflags(fflags);
                              elem
                            },
        FWV_CVT_X_F      => {
                              let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {
                                8  => { handle_illegal(); return RETIRE_FAIL },
                                16 => riscv_f16ToI32(rm_3b, vs2_val[i]),
                                32 => riscv_f32ToI64(rm_3b, vs2_val[i])
                              };
                              accrue_fflags(fflags);
                              elem
                            },
        FWV_CVT_F_XU     => {
                              let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {
                                8  => riscv_ui32ToF16(rm_3b, zero_extend(vs2_val[i])),
                                16 => riscv_ui32ToF32(rm_3b, zero_extend(vs2_val[i])),
                                32 => riscv_ui32ToF64(rm_3b, vs2_val[i])
                              };
                              accrue_fflags(fflags);
                              elem
                            },
        FWV_CVT_F_X      => {
                              let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {
                                8  => riscv_i32ToF16(rm_3b, sign_extend(vs2_val[i])),
                                16 => riscv_i32ToF32(rm_3b, sign_extend(vs2_val[i])),
                                32 => riscv_i32ToF64(rm_3b, vs2_val[i])
                              };
                              accrue_fflags(fflags);
                              elem
                            },
        FWV_CVT_F_F      => {
                              let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {
                                8  => { handle_illegal(); return RETIRE_FAIL },
                                16 => riscv_f16ToF32(rm_3b, vs2_val[i]),
                                32 => riscv_f32ToF64(rm_3b, vs2_val[i])
                              };
                              accrue_fflags(fflags);
                              elem
                            },
        FWV_CVT_RTZ_XU_F => {
                              let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {
                                8  => { handle_illegal(); return RETIRE_FAIL },
                                16 => riscv_f16ToUi32(0b001, vs2_val[i]),
                                32 => riscv_f32ToUi64(0b001, vs2_val[i])
                              };
                              accrue_fflags(fflags);
                              elem
                            },
        FWV_CVT_RTZ_X_F  => {
                              let (fflags, elem) : (bits_fflags, bits('o)) = match 'm {
                                8  => { handle_illegal(); return RETIRE_FAIL },
                                16 => riscv_f16ToI32(0b001, vs2_val[i]),
                                32 => riscv_f32ToI64(0b001, vs2_val[i])
                              };
                              accrue_fflags(fflags);
                              elem
                            }
      }
    }
  };

  write_vreg(num_elem, SEW_widen, LMUL_pow_widen, vd, result);
  vstart = zeros();
  RETIRE_SUCCESS
}