csrrwi

Atomic Read/Write CSR Immediate

This instruction is defined by:

Zicsr, version >= 0

This instruction is included in the following profiles:

Encoding

Assembly format

csrrwi rd, zimm, csr

Synopsis

Atomically write CSR using a 5-bit immediate, and load the previous value into 'rd'.

Read the old value of the CSR, zero-extends the value to XLEN bits, and then write it to integer register rd. The 5-bit uimm field is zero-extended and written to the CSR. If rd=x0, then the instruction shall not read the CSR and shall not cause any of the side effects that might occur on a CSR read.

Access

M	HS	U	VS	VU
Always	Always	Always	Always	Always

Always

Decode Variables

Bits<12> csr = $encoding[31:20];
Bits<5> imm = $encoding[19:15];
Bits<5> rd = $encoding[11:7];

Execution

IDL
Sail

if (rd != 0) {
  X[rd] = CSR[csr].sw_read();
}
CSR[csr].sw_write({{XLEN - 5{1'b0}}, imm});

{
  let rs1_val : xlenbits = if is_imm then zero_extend(rs1) else X(rs1);
  let isWrite : bool = match op {
    CSRRW  => true,
    _      => if is_imm then unsigned(rs1_val) != 0 else unsigned(rs1) != 0
  };
  if not(check_CSR(csr, cur_privilege, isWrite))
  then { handle_illegal(); RETIRE_FAIL }
  else if not(ext_check_CSR(csr, cur_privilege, isWrite))
  then { ext_check_CSR_fail(); RETIRE_FAIL }
  else {
    let csr_val = readCSR(csr); /* could have side-effects, so technically shouldn't perform for CSRW[I] with rd == 0 */
    if isWrite then {
      let new_val : xlenbits = match op {
        CSRRW => rs1_val,
        CSRRS => csr_val | rs1_val,
        CSRRC => csr_val & ~(rs1_val)
      };
      writeCSR(csr, new_val)
    };
    X(rd) = csr_val;
    RETIRE_SUCCESS
  }
}