mstatus

Machine Status

The mstatus register tracks and controls the hart’s current operating state.

Attributes

Defining Extension

  • Sm, version >= 0

CSR Address

0x300

Length

32-bit

64-bit

Privilege Mode

M

Format

This CSR format changes dynamically.

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Field Summary

Name Location Type Reset Value

SD

63

RO-H
RO-H
RO
UNDEFINED_LEGAL

MPV

39

RW-H

UNDEFINED_LEGAL

GVA

38

RW-H

0

MBE

37

RW
RO
1
0

SBE

36

RW
RO
0
1
UNDEFINED_LEGAL

SXL

35:34

RW
RO

UNDEFINED_LEGAL

UXL

33:32

RW
RO
0
1
UNDEFINED_LEGAL

TSR

22

RW

UNDEFINED_LEGAL

TW

21

RW

UNDEFINED_LEGAL

TVM

20

RO
RW
0
UNDEFINED_LEGAL
0

MXR

19

RW

UNDEFINED_LEGAL

SUM

18

RW
RO
UNDEFINED_LEGAL
0

MPRV

17

RW-H
RO

0

XS

16:15

RO

0

FS

14:13

RW-H
RO
RW
RO
UNDEFINED_LEGAL
0
UNDEFINED_LEGAL
0

MPP

12:11

RW-H

UNDEFINED_LEGAL

VS

10:9

RW-H

UNDEFINED_LEGAL

SPP

8

RW-H

UNDEFINED_LEGAL

MPIE

7

RW-H

UNDEFINED_LEGAL

UBE

6

RW
RO
0
1
UNDEFINED_LEGAL

SPIE

5

RW-H
RO
UNDEFINED_LEGAL
0

MIE

3

RW-H

0

SIE

1

RW-H
RO
UNDEFINED_LEGAL
0

Fields

SD

Location

63

Description

State Dirty.

Read-only bit that summarizes whether either the FS, XS, or VS
fields signal the presence of some dirty state.

Type
RO-H
RO-H
RO
Reset value
UNDEFINED_LEGAL

MPV

MPV is only defined in RV64 (CSR[misa].MXL == 1)
Location

39

Description

Machine Previous Virtualization mode

Written with the prior virtualization mode when entering M-mode from an exception/interrupt.
When returning via an MRET instruction, the virtualization mode becomes the value of MPV unless MPP=3, in which case the virtualization mode is always 0.
Can also be written by software.

Type

RW-H

Reset value

UNDEFINED_LEGAL

GVA

GVA is only defined in RV64 (CSR[misa].MXL == 1)
Location

38

Description

Guest Virtual Address

When a trap is taken and a guest virtual address is written into mtval, GVA is set.
When a trap is taken and a guest virtual address is written into mtval, GVA is cleared.

Type

RW-H

Reset value

0

MBE

MBE is only defined in RV64 (CSR[misa].MXL == 1)
Location

37

Description

M-mode Big Endian

Controls the endianness of data M-mode (0 = little, 1 = big).
Instructions are always little endian, regardless of the data setting.

[when,"M_MODE_ENDIANESS == little"]
Since the CPU does not support big endian, this is hardwired to 0.

[when,"M_MODE_ENDIANESS == big"]
Since the CPU does not support little endian, this is hardwired to 1.

Type
RW
RO
Reset value
1
0

SBE

SBE is only defined in RV64 (CSR[misa].MXL == 1)
Location

36

Description

S-mode Big Endian

Controls the endianness of S-mode (0 = little, 1 = big).
Instructions are always little endian, regardless of the data setting.

[when,"S_MODE_ENDIANESS == little"]
Since the CPU does not support big endian, this is hardwired to 0.

[when,"S_MODE_ENDIANESS == big"]
Since the CPU does not support litte endian, this is hardwired to 1.

Type
RW
RO
Reset value
0
1
UNDEFINED_LEGAL

SXL

SXL is only defined in RV64 (CSR[misa].MXL == 1)
Location

35:34

Description

S-mode XLEN

Sets the effective XLEN for S-mode (0 = 32-bit, 1 = 64-bit, 2 = 128-bit [reserved]).

[when,"SXLEN==32"]
Since the CPU only supports SXLEN==32, this is hardwired to 0.

[when,"SXLEN==32"]
Since the CPU only supports SXLEN==64, this is hardwired to 1.

[when,"SXLEN=3264"] + — + It is not valid to have SXLEN less than UXLEN.

It is UNDEFINED_LEGAL what will happen if a software sets mstatus.SXL to be greater than mstatus.UXL.

It is UNDEFINED_LEGAL to set the MSB of SXL. + — +

Type
RW
RO
Reset value

UNDEFINED_LEGAL

UXL

UXL is only defined in RV64 (CSR[misa].MXL == 1)
Location

33:32

Description

U-mode XLEN.

Sets the effective XLEN for U-mode (0 = 32-bit, 1 = 64-bit, 2 = 128-bit [reserved]).

[when,"UXLEN == 32"]
Since the CPU only supports UXLEN==32, this is hardwired to 0.

[when,"UXLEN == 64"]
Since the CPU only supports UXLEN==64, this is hardwired to 1.


[when,"UXLEN == 3264"] + — + It is not valid to have SXLEN less than UXLEN.

It is UNDEFINED_LEGAL what will happen if a software sets mstatus.SXL to be greater than mstatus.UXL.

It is UNDEFINED_LEGAL to set the MSB of UXL. + — +

Type
RW
RO
Reset value
0
1
UNDEFINED_LEGAL

TSR

Location

22

Description

Trap SRET

When 1, attempts to execute the sret instruction while executing in HS/S-mode
will raise an Illegal Instruction exception.

[when,"ext?(:H)"]
Does not affect the behavior of sret in VS_mode (see hstatus.VTSR).

Type

RW

Reset value

UNDEFINED_LEGAL

TW

Location

21

Description

Timeout Wait

When 1, the WFI instruction will raise an Illegal Instruction trap after an
implementaion-defined wait period when executed in a mode other than M-mode.

When 0, the wfi instruction is permitted to wait forever in (H)S-mode but must
trap after an implementation-defined wait period in U-mode.

Type

RW

Reset value

UNDEFINED_LEGAL

TVM

Location

20

Description

Trap Virtual Memory.

When 1, an Illegal Instruction trap occurs when

Type
RO
RW
Reset value
0
UNDEFINED_LEGAL
0

MXR

Location

19

Description

Make eXecutable Readable.

When 1, loads from pages marked readable or executable are allowed.
When 0, loads from pages marked executable raise a Page Fault exception.

Type

RW

Reset value

UNDEFINED_LEGAL

SUM

Location

18

Description

permit Supervisor Memory Access.

When 0, an S-mode read or an M-mode read with mstatus.MPRV=1 and mstatus.MPP=01
to a 'U' (user) page will cause an ILLEGAL INSTRUCTION exception.

Type
RW
RO
Reset value
UNDEFINED_LEGAL
0

MPRV

Location

17

Description

Modify PRiVilege.

When 1, loads and stores behave as if the current virutalization mode:privilege level was
mstatus.MPV:mstatus.MPP.

mstatus.MPRV is cleared on any exception return (mret or sret instruction, regardless of the trap handler privilege mode).

Type
RW-H
RO
Reset value

0

XS

Location

16:15

Description

Custom (X) extension context Status

Summarizes the current state of any custom extension state.
Either 0 - Off, 1 - Initial, 2 - Clean, 3 - Dirty.
Since there are no custom extensions in the base spec, this field is read-only 0.

Type

RO

Reset value

0

FS

Location

14:13

Description

Floating point context status.

When 0, floating point instructions (from F and D extensions) are disabled,
and cause ILLEGAL INSTRUCTION exceptions.
When a floating point register, or the fCSR register is written, FS obtains the value 3.
Values 1 and 2 are valid write values for software, but are not interpreted by hardware
other than to possibly enable a previously-disabled floating point unit.

Type
RW-H
RO
RW
RO
Reset value
UNDEFINED_LEGAL
0
UNDEFINED_LEGAL
0

MPP

Location

12:11

Description

M-mode Previous Privilege.

Written by hardware in two cases:

  • Written with the prior nominal privilege level when entering M-mode from an exception/interrupt.

  • Written with 0 when executing an mret instruction to return from an exception in M-mode.

    Can also be written by software without immediate side-effect.

    Affects execution in two cases:

  • On a return from an exception from M-mode, the machine will
    enter the privilege level stored in MPP before clearing the field.

  • When mstatus.MPRV is set, loads and stores behave as if the current privlege level were MPP.

Type

RW-H

Reset value

UNDEFINED_LEGAL

VS

Location

10:9

Description

Vector context status.

When 0, vector instructions (from the V extension) are disabled, and cause ILLEGAL INSTRUCTION exceptions.
When a vector register or vector CSR is written, VS obtains the value 3.
Values 1 and 2 are valid write values for software, but are not interpreted by hardware
other than to possibly enable a previously-disabled vector unit.

Type

RW-H

Reset value

UNDEFINED_LEGAL

SPP

Location

8

Description

S-mode Previous Privilege

Written by hardware in two cases:

  • Written with the prior nominal privilege level when entering (H)S-mode from an exception/interrupt.

  • Written with 0 when executing an sret instruction to return from an exception in (H)S-mode or (unlikely) M-mode.

    Can also be written by software without immediate side-effect.

    Affects execution in one case:

  • On a return from an exception using the sret instruction in (H)S-mode or (unlikely) M-mode,
    the machine will enter the privilege level stored in SPP before clearing the field.

    Notably, mstatus.SPP does not affect exception return in VS-mode (see vsstatus.SPP).

Type

RW-H

Reset value

UNDEFINED_LEGAL

MPIE

Location

7

Description

M-mode Previous Interrupt Enable

Written by hardware in two cases:

  • Written with prior value of mstatus.MIE when entering M-mode from an exception/interrupt.

  • Writen with the value 1 when returning from an exception in M-mode (via the mret instruction).

    Can also be written by software without immediate side effect.

    Other than serving as a record of nested traps as described above, mstatus.MPIE does not affect execution.

Type

RW-H

Reset value

UNDEFINED_LEGAL

UBE

Location

6

Description

U-mode Big Endian

Controls the endianness of U-mode (0 = little, 1 = big).
Instructions are always little endian, regardless of the data setting.

[when,"U_MODE_ENDIANESS == 'little'"]
Since the CPU does not support big endian in U-mode, this is hardwired to 0.

[when,"U_MODE_ENDIANESS == 'big'"]
Since the CPU does not support litte endian in U-mode, this is hardwired to 1.

Type
RW
RO
Reset value
0
1
UNDEFINED_LEGAL

SPIE

Location

5

Description

S-mode Previous Interrupt Enable

Written by hardware in two cases:

  • Written with prior value of mstatus.SIE when entering (H)S-mode from an exception/interrupt.

  • Writen with the value 1 when returning from an exception via the sret instruction in (H)S-mode or (unlikely) M-mode.

    Can also be written by software without immediate side effect.

    Other than serving as a record of nested traps as described above, mstatus.SPIE does not affect execution.

Type
RW-H
RO
Reset value
UNDEFINED_LEGAL
0

MIE

Location

3

Description

M-mode Interrupt Enable

Written by hardware in two cases:

  • Written with the value 0 when entering M-mode from an exception/interrupt.

  • Written with the prior value of mstatus.MPIE when returning from an exeception in M-mode (via mret).

    Affects execution by:

  • When 0, all interrupts are disabled when the current privilege level is M.

  • When 1, interrupts that are not otherwise disabled with a field in mie are enabled.

Type

RW-H

Reset value

0

SIE

Location

1

Description

S-mode Interrupt Enable

Written by hardware in two cases:

  • Written with the value 0 when entering (H)S-mode from an exception/interrupt.

  • Written with the prior value of mstatus.SPIE when returning from an exeception via sret in (H)S-mode or (unlikely) M-mode.

    Affects execution by:

  • When 0, all (H)S-mode interrupts are disabled when the current privilege level is (H)S (M-mode interrupts are still enabled).

  • When 1, (H)S-mode interrupts that are not otherwise disabled with a field in sie are enabled.

Type
RW-H
RO
Reset value
UNDEFINED_LEGAL
0

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

SD = csr_value.SD
MPV = csr_value.MPV
GVA = csr_value.GVA
MBE = csr_value.MBE
SBE = csr_value.SBE
SXL = if (csr_value.SXL < csr_value.UXL) {
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else if (csr_value.SXL > 1) {
  # SXL != [0, 1] is not defined (2 reserved for RV128, but that isn't ratified)
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else {
  return csr_value.SXL;
}

UXL = if (csr_value.SXL < csr_value.UXL) {
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else if (csr_value.UXL > 1) {
  # UXL != [0, 1] is not defined (2 reserved for RV128, but that isn't ratified)
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else {
  return csr_value.UXL;
}

TSR = csr_value.TSR
TW = csr_value.TW
TVM = if (CSR[misa].S == 1'b0) {
  return 0;
} else if (MSTATUS_TVM_IMPLEMENTED) {
  return csr_value.TVM;
} else {
  return 0;
}

MXR = csr_value.MXR
SUM = csr_value.SUM
MPRV = csr_value.MPRV
XS = csr_value.XS
FS = if (CSR[misa].F == 1'b1){
  return ary_includes?<$array_size(MSTATUS_FS_LEGAL_VALUES), 2>(MSTATUS_FS_LEGAL_VALUES, csr_value.FS) ? csr_value.FS : UNDEFINED_LEGAL_DETERMINISTIC;
} else if ((CSR[misa].S == 1'b0) && (CSR[misa].F == 1'b0)) {
  # must be read-only-0
  return 0;
} else {
  # there will be no hardware update in this case because we know the F extension isn't implemented
  return ary_includes?<$array_size(MSTATUS_FS_LEGAL_VALUES), 2>(MSTATUS_FS_LEGAL_VALUES, csr_value.FS) ? csr_value.FS : UNDEFINED_LEGAL_DETERMINISTIC;
}

MPP = if (csr_value.MPP == 2'b01 && !implemented?(ExtensionName::S)) {
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else if (csr_value.MPP == 2'b00 && !implemented?(ExtensionName::U)) {
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else if (csr_value.MPP == 2'b10) {
  # never a valid value
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else {
  return csr_value.MPP;
}

VS = if (CSR[misa].V == 1'b1){
  return ary_includes?<$array_size(MSTATUS_VS_LEGAL_VALUES), 2>(MSTATUS_VS_LEGAL_VALUES, csr_value.FS) ? csr_value.FS : UNDEFINED_LEGAL_DETERMINISTIC;
} else if ((CSR[misa].S == 1'b0) && (CSR[misa].V == 1'b0)) {
  # must be read-only-0
  return 0;
} else {
  # there will be no hardware update in this case because we know the V extension isn't implemented
  return ary_includes?<$array_size(MSTATUS_VS_LEGAL_VALUES), 2>(MSTATUS_VS_LEGAL_VALUES, csr_value.FS) ? csr_value.FS : UNDEFINED_LEGAL_DETERMINISTIC;
}

SPP = if (csr_value.SPP == 2'b10) {
  return UNDEFINED_LEGAL_DETERMINISTIC;
} else {
  return csr_value.SPP;
}

MPIE = csr_value.MPIE
UBE = csr_value.UBE
SPIE = csr_value.SPIE
MIE = csr_value.MIE
SIE = csr_value.SIE