vnsra.wi
No synopsis available.
This instruction is defined by:
-
V, version >= 0
This instruction is included in the following profiles:
-
RVA22U64 (Optional)
Decode Variables
Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> simm5 = $encoding[19:15];
Bits<5> vd = $encoding[11:7];Execution
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IDL
-
Sail
{
let SEW = get_sew();
let LMUL_pow = get_lmul_pow();
let num_elem = get_num_elem(LMUL_pow, SEW);
let SEW_widen = SEW * 2;
let LMUL_pow_widen = LMUL_pow + 1;
if illegal_variable_width(vd, vm, SEW_widen, LMUL_pow_widen) |
not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))
then { handle_illegal(); return RETIRE_FAIL };
let 'n = num_elem;
let 'm = SEW;
let 'o = SEW_widen;
let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);
let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);
let imm_val : bits('m) = sign_extend(simm);
let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);
result : vector('n, dec, bits('m)) = undefined;
mask : vector('n, dec, bool) = undefined;
(result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);
assert(SEW_widen <= 64);
foreach (i from 0 to (num_elem - 1)) {
if mask[i] then {
result[i] = match funct6 {
NIS_VNSRL => {
let shift_amount = get_shift_amount(imm_val, SEW_widen);
slice(vs2_val[i] >> shift_amount, 0, SEW)
},
NIS_VNSRA => {
let shift_amount = get_shift_amount(imm_val, SEW_widen);
let v_double : bits('o * 2) = sign_extend(vs2_val[i]);
let arith_shifted : bits('o) = slice(v_double >> shift_amount, 0, SEW_widen);
slice(arith_shifted, 0, SEW)
}
}
}
};
write_vreg(num_elem, SEW, LMUL_pow, vd, result);
vstart = zeros();
RETIRE_SUCCESS
}