fcvt.w.s

Convert single-precision float to integer word to signed 32-bit integer.

This instruction is defined by:

F, version >= 0

This instruction is included in the following profiles:

RVA20S64 (Mandatory)
RVA20U64 (Mandatory)
RVA22S64 (Mandatory)
RVA22U64 (Mandatory)

Encoding

Assembly format

fcvt.w.s rd, fs1

Synopsis

This instruction must have data-independent timing when extension Zkt is enabled.

Converts a floating-point number in floating-point register fs1 to a signed 32-bit integer indicates integer register rd.

For XLEN >32, fcvt.w.s sign-extends the 32-bit result to the destination register width.

If the rounded result is not representable as a 32-bit signed integer, it is clipped to the nearest value and the invalid flag is set.

The range of valid inputs and behavior for invalid inputs are:

Value

	Value
Minimum valid input (after rounding)	`-2^31`
Maximum valid input (after rounding)	`2^31 - 1`
Output for out-of-range negative input	`-2^31`
Output for `-∞`	`-2^31`
Output for out-of-range positive input	`2^31 - 1`
Output for `+∞` for `NaN`	`2^31 - 1`

Minimum valid input (after rounding)

-2^31

Maximum valid input (after rounding)

2^31 - 1

Output for out-of-range negative input

-2^31

Output for -∞

-2^31

Output for out-of-range positive input

2^31 - 1

Output for +∞ for NaN

2^31 - 1

All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using fcvt.s.w rd, x0, which will never set any exception flags.

All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set.

Access

M	HS	U	VS	VU
Always	Always	Always	Always	Always

Always

Decode Variables

Bits<5> fs1 = $encoding[19:15];
Bits<3> rm = $encoding[14:12];
Bits<5> rd = $encoding[11:7];

Execution

IDL
Sail

check_f_ok($encoding);
Bits<32> sp_value = f[fs1][31:0];
Bits<1> sign = sp_value[31];
Bits<8> exp = sp_value[30:23];
Bits<23> sig = sp_value[22:0];
RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
if ((exp == 0xff) && (sig != 0)) {
  sign = 0;
  set_fp_flag(FpFlag::NV);
  X[rd] = SP_CANONICAL_NAN;
} else {
  if (exp != 0) {
    sig = sig | 0x00800000;
  }
  Bits<64> sig64 = sig << 32;
  Bits<16> shift_dist = 0xAA - exp;
  if (0 < shift_dist) {
    sig64 = softfloat_shiftRightJam64(sig64, shift_dist);
  }
  X[rd] = softfloat_roundToI32(sign, sig64, rounding_mode);
}

{
  assert(sizeof(xlen) >= 64);
  let rs1_val_LU = X(rs1)[63..0];
  match (select_instr_or_fcsr_rm (rm)) {
    None() => { handle_illegal(); RETIRE_FAIL },
    Some(rm') => {
      let rm_3b = encdec_rounding_mode(rm');
      let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU);

      accrue_fflags(fflags);
      F_or_X_S(rd) = rd_val_S;
      RETIRE_SUCCESS
    }
  }
}

Exceptions

This instruction may result in the following synchronous exceptions:

IllegalInstruction