Bits to inhibit (stops counting) performance counters.
The counter-inhibit register mcountinhibit is a WARL register that
controls which of the hardware performance-monitoring counters
increment. The settings in this register only control whether the
counters increment; their accessibility is not affected by the setting
of this register.
When the CY, IR, or HPMn bit in the mcountinhibit register is clear,
the mcycle, minstret, or mhpmcountern register increments as usual.
When the CY, IR, or HPM_n_ bit is set, the corresponding counter does
not increment.
The mcycle CSR may be shared between harts on the same core, in which
case the mcountinhibit.CY field is also shared between those harts,
and so writes to mcountinhibit.CY will be visible to those harts.
If the mcountinhibit register is not implemented, the implementation
behaves as though the register were set to zero.
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When the mcycle and minstret counters are not needed, it is desirable
to conditionally inhibit them to reduce energy consumption. Providing a
single CSR to inhibit all counters also allows the counters to be
atomically sampled.
Because the mtime counter can be shared between multiple cores, it
cannot be inhibited with the mcountinhibit mechanism.
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