vfncvt.rtz.xu.f.w
No synopsis available.
This instruction is defined by:
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V, version >= 0
This instruction is included in the following profiles:
-
RVA22S64 (Optional)
-
RVA22U64 (Optional)
Decode Variables
Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> vd = $encoding[11:7];Execution
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IDL
-
Sail
{
let rm_3b = fcsr.FRM();
let SEW = get_sew();
let LMUL_pow = get_lmul_pow();
let num_elem = get_num_elem(LMUL_pow, SEW);
let SEW_widen = SEW * 2;
let LMUL_pow_widen = LMUL_pow + 1;
if illegal_fp_variable_width(vd, vm, SEW, rm_3b, SEW_widen, LMUL_pow_widen) |
not(valid_reg_overlap(vs2, vd, LMUL_pow_widen, LMUL_pow))
then { handle_illegal(); return RETIRE_FAIL };
let 'n = num_elem;
let 'm = SEW;
let 'o = SEW_widen;
let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);
let vs2_val : vector('n, dec, bits('o)) = read_vreg(num_elem, SEW_widen, LMUL_pow_widen, vs2);
let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);
result : vector('n, dec, bits('m)) = undefined;
mask : vector('n, dec, bool) = undefined;
(result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);
foreach (i from 0 to (num_elem - 1)) {
if mask[i] then {
result[i] = match vfnunary0 {
FNV_CVT_XU_F => {
let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {
8 => riscv_f16ToUi8(rm_3b, vs2_val[i]),
16 => riscv_f32ToUi16(rm_3b, vs2_val[i]),
32 => riscv_f64ToUi32(rm_3b, vs2_val[i])
};
accrue_fflags(fflags);
elem
},
FNV_CVT_X_F => {
let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {
8 => riscv_f16ToI8(rm_3b, vs2_val[i]),
16 => riscv_f32ToI16(rm_3b, vs2_val[i]),
32 => riscv_f64ToI32(rm_3b, vs2_val[i])
};
accrue_fflags(fflags);
elem
},
FNV_CVT_F_XU => {
let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {
8 => { handle_illegal(); return RETIRE_FAIL },
16 => riscv_ui32ToF16(rm_3b, vs2_val[i]),
32 => riscv_ui64ToF32(rm_3b, vs2_val[i])
};
accrue_fflags(fflags);
elem
},
FNV_CVT_F_X => {
let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {
8 => { handle_illegal(); return RETIRE_FAIL },
16 => riscv_i32ToF16(rm_3b, vs2_val[i]),
32 => riscv_i64ToF32(rm_3b, vs2_val[i])
};
accrue_fflags(fflags);
elem
},
FNV_CVT_F_F => {
let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {
8 => { handle_illegal(); return RETIRE_FAIL },
16 => riscv_f32ToF16(rm_3b, vs2_val[i]),
32 => riscv_f64ToF32(rm_3b, vs2_val[i])
};
accrue_fflags(fflags);
elem
},
FNV_CVT_ROD_F_F => {
let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {
8 => { handle_illegal(); return RETIRE_FAIL },
16 => riscv_f32ToF16(0b110, vs2_val[i]),
32 => riscv_f64ToF32(0b110, vs2_val[i])
};
accrue_fflags(fflags);
elem
},
FNV_CVT_RTZ_XU_F => {
let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {
8 => riscv_f16ToUi8(0b001, vs2_val[i]),
16 => riscv_f32ToUi16(0b001, vs2_val[i]),
32 => riscv_f64ToUi32(0b001, vs2_val[i])
};
accrue_fflags(fflags);
elem
},
FNV_CVT_RTZ_X_F => {
let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {
8 => riscv_f16ToI8(0b001, vs2_val[i]),
16 => riscv_f32ToI16(0b001, vs2_val[i]),
32 => riscv_f64ToI32(0b001, vs2_val[i])
};
accrue_fflags(fflags);
elem
}
}
}
};
write_vreg(num_elem, SEW, LMUL_pow, vd, result);
vstart = zeros();
RETIRE_SUCCESS
}