mip

1

Supervisor Software Interrupt Pending

Reports the current pending state of an (H)S-mode software interrupt, which is generated by writing to this field.


Alias:

RW

0

2

Virtual Supervisor Software Interrupt Pending

Reports the current pending state of a VS-mode software interrupt, which is generated by writing to this field.


Aliases:

RW

0

3

Machine Software Interrupt Pending

Unused field.

RO

0

5

Supervisor Timer Interrupt Pending

Reports the current pending state of an (H)S-mode timer interrupt
, which is generated by software by writing to mip.STIP.


Alias:

RW

0

6

Virtual Supervisor Timer Interrupt Pending

Reports the current pending state of a VS-mode timer interrupt
, which is generated by M-mode and/or HS-mode software by writing to hvip.VSTIP.


mip.VSTIP is never writable. If VS-mode software wants to clear the bit, it must do so
by calling into the hypervisor (which can then clear hvip.VSTIP).

Aliases:

RO-H

0

7

Machine Timer Interrupt Pending

Reports the current pending state of an M-mode timer interrupt.

Bit is controlled by the timer device (using mtimecmp), and is not writeable.

RO-H

0

9

Supervisor External Interrupt Pending

Reports the current pending state of an (H)S-mode external interrupt.

This field has two parts: a software-writeable shadow value and a wire from the interrupt controller.
The value presented to software in the bit on a CSR read is the logical OR of the software-writeable value and the interrupt controller value.
When software writes this bit, only the shadow value is updated (the interrupt controller is not notified of the write).


Alias:

RW-H

0

10

Virtual Supervisor External Interrupt Pending

Reports the current pending state of a VS-mode external interrupt.

This field is the logical OR of hvip.VSEIP and the wire coming from the interrupt controller.

The field is not writable by software

RO-H

0

11

Machine External Interrupt Pending

Reports the current pending state of an M-mode external interrupt.

MEIP is controlled by the external interrupt controller .
It is not writable by software.

RO-H

0

12

Supervisor Guest External Interrupt Pending

Read-only summary of any pending Supervisor Guest External Interrupt Pending, i.e.:
the logical-OR reduction of the hgeip register.

Alias:

RO-H

0

13

Local Counter Overflow Interrupt pending


When a counter overflow interrupt occurs, a hidden sticky bit is set.

Software writes 0 to mip.LCOFIP to clear the pending interrupt.

Alias:

RW-H

0