vfrec7.v
No synopsis available.
This instruction is defined by:
-
V, version >= 0
This instruction is included in the following profiles:
-
RVA22U64 (Optional)
Decode Variables
Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> vd = $encoding[11:7];
Execution
-
IDL
-
Sail
{
let rm_3b = fcsr.FRM();
let SEW = get_sew();
let LMUL_pow = get_lmul_pow();
let num_elem = get_num_elem(LMUL_pow, SEW);
if illegal_fp_normal(vd, vm, SEW, rm_3b) then { handle_illegal(); return RETIRE_FAIL };
assert(SEW != 8);
let 'n = num_elem;
let 'm = SEW;
let vm_val : vector('n, dec, bool) = read_vmask(num_elem, vm, 0b00000);
let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vs2);
let vd_val : vector('n, dec, bits('m)) = read_vreg(num_elem, SEW, LMUL_pow, vd);
result : vector('n, dec, bits('m)) = undefined;
mask : vector('n, dec, bool) = undefined;
(result, mask) = init_masked_result(num_elem, SEW, LMUL_pow, vd_val, vm_val);
foreach (i from 0 to (num_elem - 1)) {
if mask[i] then {
result[i] = match vfunary1 {
FVV_VSQRT => {
let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {
16 => riscv_f16Sqrt(rm_3b, vs2_val[i]),
32 => riscv_f32Sqrt(rm_3b, vs2_val[i]),
64 => riscv_f64Sqrt(rm_3b, vs2_val[i])
};
accrue_fflags(fflags);
elem
},
FVV_VRSQRT7 => {
let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {
16 => riscv_f16Rsqrte7(rm_3b, vs2_val[i]),
32 => riscv_f32Rsqrte7(rm_3b, vs2_val[i]),
64 => riscv_f64Rsqrte7(rm_3b, vs2_val[i])
};
accrue_fflags(fflags);
elem
},
FVV_VREC7 => {
let (fflags, elem) : (bits_fflags, bits('m)) = match 'm {
16 => riscv_f16Recip7(rm_3b, vs2_val[i]),
32 => riscv_f32Recip7(rm_3b, vs2_val[i]),
64 => riscv_f64Recip7(rm_3b, vs2_val[i])
};
accrue_fflags(fflags);
elem
},
FVV_VCLASS => fp_class(vs2_val[i])
}
}
};
write_vreg(num_elem, SEW, LMUL_pow, vd, result);
vstart = zeros();
RETIRE_SUCCESS
}