F Extension
Versions
- 2.2.0
-
- State
-
ratified
- Ratification date
-
2019-12
- Changes
-
-
Define NaN-boxing scheme, changed definition of FMAX and FMIN
-
Synopsis
This chapter describes the standard instruction-set extension for single-precision floating-point, which is named "F" and adds single-precision floating-point computational instructions compliant with the IEEE 754-2008 arithmetic standard cite:[ieee754-2008]. The F extension depends on the "Zicsr" extension for control and status register access.
F Register State
The F extension adds 32 floating-point registers, f0-f31
, each 32
bits wide, and a floating-point control and status register fcsr,
which contains the operating mode and exception status of the
floating-point unit. This additional state is shown in
RISC-V standard F extension single-precision floating-point state. We use the term FLEN to describe the width of
the floating-point registers in the RISC-V ISA, and FLEN=32 for the F
single-precision floating-point extension. Most floating-point
instructions operate on values in the floating-point register file.
Floating-point load and store instructions transfer floating-point
values between registers and memory. Instructions to transfer values to and from the integer register file are also provided.
We considered a unified register file for both integer and floating-point values as this simplifies software register allocation and calling conventions, and reduces total user state. However, a split organization increases the total number of registers accessible with a given instruction width, simplifies provision of enough regfile ports for wide superscalar issue, supports decoupled floating-point-unit architectures, and simplifies use of internal floating-point encoding techniques. Compiler support and calling conventions for split register file architectures are well understood, and using dirty bits on floating-point register file state can reduce context-switch overhead. |
FLEN-1 | 0 | |
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f0 |
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f1 |
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f2 |
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f3 |
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f4 |
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f5 |
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f6 |
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f7 |
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f8 |
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f9 |
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f10 |
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f11 |
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f12 |
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f13 |
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f14 |
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f15 |
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f16 |
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f17 |
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f18 |
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f19 |
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f20 |
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f21 |
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f22 |
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f23 |
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f24 |
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f25 |
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f26 |
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f27 |
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f28 |
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f29 |
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f30 |
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f31 |
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FLEN |
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31 |
0 |
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fcsr |
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32 |
Floating-Point Control and Status Register
The floating-point control and status register, fcsr, is a RISC-V control and status register (CSR). It is a 32-bit read/write register that selects the dynamic rounding mode for floating-point arithmetic operations and holds the accrued exception flags, as shown in Floating-Point Control and Status Register.
Unresolved include directive in modules/exts/pages/F.adoc - include::images/wavedrom/float-csr.adoc[]
The fcsr register can be read and written with the FRCSR and FSCSR instructions, which are assembler pseudoinstructions built on the underlying CSR access instructions. FRCSR reads fcsr by copying it into integer register rd. FSCSR swaps the value in fcsr by copying the original value into integer register rd, and then writing a new value obtained from integer register rs1 into fcsr.
The fields within the fcsr can also be accessed individually through
different CSR addresses, and separate assembler pseudoinstructions are defined
for these accesses. The FRRM instruction reads the Rounding Mode field frm
(fcsr bits 7—5) and copies it into the least-significant three bits of
integer register rd, with zero in all other bits. FSRM swaps the value in
frm
by copying the original value into integer register rd, and then
writing a new value obtained from the three least-significant bits of integer
register rs1 into frm
. FRFLAGS and FSFLAGS are defined analogously for the
Accrued Exception Flags field fflags
(fcsr bits 4—0).
Bits 31—8 of the fcsr are reserved for other standard extensions. If these extensions are not present, implementations shall ignore writes to these bits and supply a zero value when read. Standard software should preserve the contents of these bits.
Floating-point operations use either a static rounding mode encoded in
the instruction, or a dynamic rounding mode held in frm
. Rounding
modes are encoded as shown in Rounding mode encoding.. A value of 111 in the
instruction’s rm field selects the dynamic rounding mode held in
frm
. The behavior of floating-point instructions that depend on
rounding mode when executed with a reserved rounding mode is reserved, including both static reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111). Some instructions, including widening conversions, have the rm field but are nevertheless mathematically unaffected by the rounding mode; software should set their rm field to
RNE (000) but implementations must treat the rm field as usual (in
particular, with regard to decoding legal vs. reserved encodings).
Rounding Mode | Mnemonic | Meaning |
---|---|---|
000 |
RNE |
Round to Nearest, ties to Even |
001 |
RTZ |
Round towards Zero |
010 |
RDN |
Round Down (towards \(-\infty\)) |
011 |
RUP |
Round Up (towards \(+\infty\)) |
100 |
RMM |
Round to Nearest, ties to Max Magnitude |
101 |
Reserved for future use. |
|
110 |
Reserved for future use. |
|
111 |
DYN |
In instruction’s rm field, selects dynamic rounding mode; In Rounding Mode register, reserved. |
The C99 language standard effectively mandates the provision of a dynamic rounding mode register. In typical implementations, writes to the dynamic rounding mode CSR state will serialize the pipeline. Static rounding modes are used to implement specialized arithmetic operations that often have to switch frequently between different rounding modes. The ratified version of the F spec mandated that an illegal-instruction exception was raised when an instruction was executed with a reserved dynamic rounding mode. This has been weakened to reserved, which matches the behavior of static rounding-mode instructions. Raising an illegal-instruction exception is still valid behavior when encountering a reserved encoding, so implementations compatible with the ratified spec are compatible with the weakened spec. |
The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic instruction since the field was last reset by software, as shown in Accrued exception flag encoding.. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag.
Flag Mnemonic | Flag Meaning |
---|---|
NV |
Invalid Operation |
DZ |
Divide by Zero |
OF |
Overflow |
UF |
Underflow |
NX |
Inexact |
As allowed by the standard, we do not support traps on floating-point exceptions in the F extension, but instead require explicit checks of the flags in software. We considered adding branches controlled directly by the contents of the floating-point accrued exception flags, but ultimately chose to omit these instructions to keep the ISA simple. |
NaN Generation and Propagation
Except when otherwise stated, if the result of a floating-point
operation is NaN, it is the canonical NaN. The canonical NaN has a
positive sign and all significand bits clear except the MSB, a.k.a. the
quiet bit. For single-precision floating-point, this corresponds to the pattern 0x7fc00000
.
We considered propagating NaN payloads, as is recommended by the standard, but this decision would have increased hardware cost. Moreover, since this feature is optional in the standard, it cannot be used in portable code. Implementors are free to provide a NaN payload propagation scheme as a nonstandard extension enabled by a nonstandard operating mode. However, the canonical NaN scheme described above must always be supported and should be the default mode. |
We require implementations to return the standard-mandated default values in the case of exceptional conditions, without any further intervention on the part of user-level software (unlike the Alpha ISA floating-point trap barriers). We believe full hardware handling of exceptional cases will become more common, and so wish to avoid complicating the user-level ISA to optimize other approaches. Implementations can always trap to machine-mode software handlers to provide exceptional default values. |
Subnormal Arithmetic
Operations on subnormal numbers are handled in accordance with the IEEE 754-2008 standard.
In the parlance of the IEEE standard, tininess is detected after rounding.
Detecting tininess after rounding results in fewer spurious underflow signals. |
Instructions
The following instructions are defined by this extension:
No synopsis available. |
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Single-precision floating-point classify. |
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No synopsis available. |
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No synopsis available. |
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No synopsis available. |
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No synopsis available. |
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Convert signed 32-bit integer to single-precision float |
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No synopsis available. |
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Convert single-precision float to integer word to signed 32-bit integer. |
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No synopsis available. |
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No synopsis available. |
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Single-precision floating-point equal |
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Single-precision floating-point less than or equal |
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Single-precision floating-point less than |
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Single-precision floating-point load |
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No synopsis available. |
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No synopsis available. |
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No synopsis available. |
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No synopsis available. |
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No synopsis available. |
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Half-precision floating-point move from integer |
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Single-precision floating-point move from integer |
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Move single-precision value from floating-point to integer register |
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No synopsis available. |
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No synopsis available. |
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Single-precision sign inject |
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Single-precision sign inject negate |
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Single-precision sign inject exclusive or |
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No synopsis available. |
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No synopsis available. |
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Single-precision floating-point store |
Parameters
This extension has the following implementation options:
- HW_MSTATUS_FS_DIRTY_UPDATE
-
Type
string
Valid Values
[never, precise, imprecise]
Description
Indicates whether or not hardware will write to mstatus.FS
Values are:
never
Hardware never writes mstatus.FS
precise
Hardware writes mstatus.FS to the Dirty (3) state precisely when F registers are modified
imprecise
Hardware writes mstatus.FS imprecisely. This will result in a call to unpredictable() on any attempt to read mstatus or write FP state.
- MSTATUS_FS_LEGAL_VALUES
-
Type
array
Valid Values
at most 4-element array of [0, 1, 2, 3]
Description
The set of values that mstatus.FS will accept from a software write.
- MUTABLE_MISA_F