add
Integer add
This instruction is defined by:
-
I, version >= 0
This instruction is included in the following profiles:
-
RVA20S64 (Mandatory)
-
RVA20U64 (Mandatory)
-
RVA22S64 (Mandatory)
-
RVA22U64 (Mandatory)
Synopsis
This instruction must have data-independent timing when extension Zkt is enabled. |
Add the value in rs1 to rs2, and store the result in rd. Any overflow is thrown away.
Decode Variables
Bits<5> rs2 = $encoding[24:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];
Execution
-
IDL
-
Sail
X[rd] = X[rs1] + X[rs2];
{
let rs1_val = X(rs1);
let rs2_val = X(rs2);
let result : xlenbits = match op {
RISCV_ADD => rs1_val + rs2_val,
RISCV_SLT => zero_extend(bool_to_bits(rs1_val <_s rs2_val)),
RISCV_SLTU => zero_extend(bool_to_bits(rs1_val <_u rs2_val)),
RISCV_AND => rs1_val & rs2_val,
RISCV_OR => rs1_val | rs2_val,
RISCV_XOR => rs1_val ^ rs2_val,
RISCV_SLL => if sizeof(xlen) == 32
then rs1_val << (rs2_val[4..0])
else rs1_val << (rs2_val[5..0]),
RISCV_SRL => if sizeof(xlen) == 32
then rs1_val >> (rs2_val[4..0])
else rs1_val >> (rs2_val[5..0]),
RISCV_SUB => rs1_val - rs2_val,
RISCV_SRA => if sizeof(xlen) == 32
then shift_right_arith32(rs1_val, rs2_val[4..0])
else shift_right_arith64(rs1_val, rs2_val[5..0])
};
X(rd) = result;
RETIRE_SUCCESS
}