sepc

Supervisor Exception Program Counter

Written with the PC of an instruction on an exception or interrupt taken in (H)S-mode.

Also controls where the hart jumps on an exception return from (H)S-mode.

Attributes

Defining Extension

CSR Address

0x141

Length

64-bit

Privilege Mode

Figure 1. sepc format

Name Location Type Reset Value

Name	Location	Type	Reset Value
`PC`	63:0	RW-RH	UNDEFINED_LEGAL

63:0

RW-RH

UNDEFINED_LEGAL

Location: 63:0
Description: When a trap is taken into S-mode, sepc.PC is written with the virtual address of the
instruction that was interrupted or that encountered the exception.
Otherwise, sepc.PC is never written by the implementation, though it may be explicitly written
by software.

On an exception retun from S-mode (from the SRET instruction),
control transfers to the virtual address read out of sepc.PC.

Because PCs are always word-aligned,
bits 1:0 of sepc.PC are always
read-only 0.

[when,"ext?(:C) && MUTABLE_MISA_C == true"]
When misa.C is clear, bit 1 is masked to zero. Writes to bit 1 are still captured, and
may be visible on the next read with misa.C is set.

Holds bits 63:1 of the virtual address associated with an exception.
Type: RW-RH
Reset value: UNDEFINED_LEGAL

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

PC = return csr_value.PC & ~64'b1;

This CSR may return a value that is different from what is stored in hardware.

if (implemented?(ExtensionName::C) && CSR[misa].C == 1'b1) {
  return CSR[sepc].PC & ~64'b1;
} else {
  return CSR[sepc].PC;
}