addiw

Add immediate word

This instruction is defined by:

  • I, version >= 0

This instruction is included in the following profiles:

  • MockProfile 64-bit Unpriv (Mandatory)

  • MockProfile 64-bit S-mode (Mandatory)

  • RVA20U64 (Mandatory)

  • RVA22U64 (Mandatory)

  • RVI20U32 (Mandatory)

  • RVI20U64 (Mandatory)

Encoding

svg

Assembly format

addiw rd, rs1, imm

Synopsis

This instruction must have data-independent timing when extension Zkt is enabled.

Add an immediate to the 32-bit value in rs1, and store the sign extended result in rd

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

Bits<12> imm = $encoding[31:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];

Execution

  • IDL

  • Sail

XReg operand = sext(X[rs1], 31);
X[rd] = sext(operand + imm, 31);
{
  let result : xlenbits = sign_extend(imm) + X(rs1);
  X(rd) = sign_extend(result[31..0]);
  RETIRE_SUCCESS
}