fcvt.s.w

Convert signed 32-bit integer to single-precision float

This instruction is defined by:

  • F, version >= 0

This instruction is included in the following profiles:

  • RVA20U64 (Mandatory)

  • RVA22U64 (Mandatory)

  • RVI20U32 (Optional)

  • RVI20U64 (Optional)

Encoding

svg

Assembly format

fcvt.s.w fd, rs1

Synopsis

Converts a 32-bit signed integer in integer register rs1 into a floating-point number in floating-point register fd.

All floating-point to integer and integer to floating-point conversion instructions round according to the rm field. A floating-point register can be initialized to floating-point positive zero using fcvt.s.w rd, x0, which will never set any exception flags.

All floating-point conversion instructions set the Inexact exception flag if the rounded result differs from the operand value and the Invalid exception flag is not set.

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

Bits<5> rs1 = $encoding[19:15];
Bits<3> rm = $encoding[14:12];
Bits<5> fd = $encoding[11:7];

Execution

  • IDL

  • Sail

check_f_ok($encoding);
Bits<32> int_value = X[rs1];
Bits<1> sign = int_value[31];
RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
if ((int_value & 32'h7fff_ffff) == 0) {
  X[fd] = (sign == 1) ? packToF32UI(1, 0x9E, 0) : 0;
} else {
  Bits<32> absA = (sign == 1) ? -int_value : int_value;
  X[fd] = softfloat_normRoundPackToF32(sign, 0x9C, absA, rounding_mode);
}
mark_f_state_dirty();
{
  assert(sizeof(xlen) >= 64);
  let rs1_val_LU = X(rs1)[63..0];
  match (select_instr_or_fcsr_rm (rm)) {
    None() => { handle_illegal(); RETIRE_FAIL },
    Some(rm') => {
      let rm_3b = encdec_rounding_mode(rm');
      let (fflags, rd_val_S) = riscv_ui64ToF32 (rm_3b, rs1_val_LU);

      accrue_fflags(fflags);
      F_or_X_S(rd) = rd_val_S;
      RETIRE_SUCCESS
    }
  }
}

Exceptions

This instruction may result in the following synchronous exceptions:

  • IllegalInstruction