srlw

Shift right logical word

This instruction is defined by:

I, version >= 0

This instruction is included in the following profiles:

RVA20S64 (Mandatory)
RVA20U64 (Mandatory)
RVA22S64 (Mandatory)
RVA22U64 (Mandatory)

Encoding

Assembly format

srlw rd, rs1, rs2

Synopsis

This instruction must have data-independent timing when extension Zkt is enabled.

Logical shift the 32-bit value in rs1 right by the value in the lower 5 bits of rs2, and store the sign-extended result in rd.

Access

M	HS	U	VS	VU
Always	Always	Always	Always	Always

Always

Decode Variables

Bits<5> rs2 = $encoding[24:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];

Execution

IDL
Sail

X[rd] = sext(X[rs1][31:0] >> X[rs2][4:0], 31);

{
  let rs1_val = (X(rs1))[31..0];
  let rs2_val = (X(rs2))[31..0];
  let result : bits(32) = match op {
    RISCV_ADDW => rs1_val + rs2_val,
    RISCV_SUBW => rs1_val - rs2_val,
    RISCV_SLLW => rs1_val << (rs2_val[4..0]),
    RISCV_SRLW => rs1_val >> (rs2_val[4..0]),
    RISCV_SRAW => shift_right_arith32(rs1_val, rs2_val[4..0])
  };
  X(rd) = sign_extend(result);
  RETIRE_SUCCESS
}