"Smcdeleg" Counter Delegation Extension, Version 1.0.0
In modern “Rich OS” environments, hardware performance monitoring resources are managed by the kernel, kernel driver, and/or hypervisor. Counters may be configured with differing scopes, in some cases counting events system-wide, while in others counting events on behalf of a single virtual machine or application. In such environments, the latency of counter writes has a direct impact on overall profiling overhead as a result of frequent counter writes during:
-
Sample collection, to clear overflow indication, and reload overflowed counter(s)
-
Context switch, between processes, threads, containers, or virtual machines
This extension provides a means for M-mode to allow writing select counters and event selectors from S/HS-mode. The purpose is to avert transitions to and from M-mode that add latency to these performance critical supervisor/hypervisor code sections. This extension also defines one new CSR, scountinhibit.
For a Machine-level environment, extension Smcdeleg (‘Sm’ for Privileged architecture and Machine-level extension, ‘cdeleg’ for Counter Delegation) encompasses all added CSRs and all behavior modifications for a hart, over all privilege levels. For a Supervisor-level environment, extension Ssccfg (‘Ss’ for Privileged architecture and Supervisor-level extension, ‘ccfg’ for Counter Configuration) provides access to delegated counters, and to new supervisor-level state.
Counter Delegation
The mcounteren
register allows M-mode to provide the next-lower
privilege mode with read access to select counters. When the Smcdeleg/Ssccfg
extension is enabled (menvcfg
.CDE=1), it further allows M-mode to delegate select
counters to S-mode.
The siselect
(and vsiselect
) index range 0x40-0x5F is reserved for
delegated counter access. When a counter i is delegated
(mcounteren
[i]=1 and menvcfg
.CDE=1), the register state associated
with counter i can be read or written via sireg*
, while siselect
holds
0x40+i. The counter state accessible via alias CSRs is shown in
the table below.
siselect value |
sireg |
sireg4 |
sireg2 |
sireg5 |
---|---|---|---|---|
0x40 |
|
|
|
|
0x41 |
See below |
|||
0x42 |
|
|
|
|
0x43 |
|
|
|
|
… |
… |
… |
… |
… |
0x5F |
|
|
|
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1 Depends on Zicntr support
2 Depends on Zihpm support
3 Depends on Sscofpmf support
4 Depends on Smcntrpmf support
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If extension Smstateen is implemented, refer to extension Smcsrind/Sscsrind ([indirect-csr]) for how setting bit 60 of CSR
mstateen0
to zero prevents access to registers siselect
, sireg*
,
vsiselect
, and vsireg*
from privileged modes less privileged than
M-mode, and likewise how setting bit 60 of hstateen0
to zero prevents
access to siselect
and sireg*
(really vsiselect
and vsireg*
) from
VS-mode.
The remaining rules of this section apply only when access to a CSR is
not blocked by mstateen0
[60] = 0 or hstateen0
[60] = 0.
While the privilege mode is M or S and siselect
holds a value in the
range 0x40-0x5F, illegal instruction exceptions are raised for the
following cases:
-
attempts to access any
sireg*
whenmenvcfg
.CDE = 0; -
attempts to access
sireg3
orsireg6
; -
attempts to access
sireg4
orsireg5
when XLEN = 64; -
attempts to access
sireg*
whensiselect
= 0x41, or when the counter selected bysiselect
is not delegated to S-mode (the corresponding bit inmcounteren
= 0).
The memory-mapped mtime register is not a performance monitoring
counter to be managed by supervisor software, hence the special
treatment of siselect value 0x41 described above.
|
For each siselect
and sireg*
combination defined in Indirect HPM State Mappings, the table
further indicates the extensions upon which the underlying counter state
depends. If any extension upon which the underlying state depends is not
implemented, an attempt from M or S mode to access the given state
through sireg*
raises an illegal instruction exception.
If the hypervisor (H) extension is also implemented, then as specified
by extension Smcsrind/Sscsrind, a virtual instruction exception is
raised for attempts from VS-mode or VU-mode to directly access vsiselect
or vsireg*
, or attempts from VU-mode to access siselect
or sireg*
. Furthermore, while vsiselect
holds a value in the range 0x40-0x5F:
-
An attempt to access any
vsireg*
from M or S mode raises an illegal instruction exception. -
An attempt from VS-mode to access any
sireg*
(reallyvsireg*
) raises either an illegal instruction exception ifmenvcfg
.CDE = 0, or a virtual instruction exception ifmenvcfg
.CDE = 1.
If Sscofpmf is implemented, sireg2
and sireg5
provide access only to a
subset of the event selector registers. Specifically, event selector bit
62 (MINH) is read-only 0 when accessed through sireg*
. Similarly, if
Smcntrpmf is implemented, sireg2
and sireg5
provide access only to a
subset of the counter configuration registers. Counter configuration
register bit 62 (MINH) is read-only 0 when accessed through sireg*
.
Supervisor Counter Inhibit Register (scountinhibit
)
Smcdeleg/Ssccfg defines a new scountinhibit
register, a masked alias of
mcountinhibit
. For counters delegated to S-mode, the associated
mcountinhibit
bits can be accessed via scountinhibit
. For counters not
delegated to S-mode, the associated bits in scountinhibit
are read-only
zero.
When menvcfg
.CDE=0, attempts to access scountinhibit
raise an illegal
instruction exception. When the Supervisor Counter Delegation extension
is enabled, attempts to access scountinhibit
from VS-mode or VU-mode
raise a virtual instruction exception.
Virtualizing scountovf
For implementations that support Smcdeleg/Ssccfg, Sscofpmf, and the H
extension, when menvcfg
.CDE=1, attempts to access scountovf
from VS-mode
or VU-mode raise a virtual instruction exception.
Virtualizing Local Counter Overflow Interrupts
For implementations that support Smcdeleg, Smcofpmf, and Smaia, the
local counter overflow interrupt (LCOFI) bit (bit 13) in each of CSRs
mvip
and mvien
is implemented and writable.
For implementations that support Smcdeleg/Ssccfg, Smcofpmf/Sscofpmf,
Smaia/Ssaia, and the H extension, the LCOFI bit (bit 13) in each of hvip
and hvien
is implemented and writable.
The By virtue of implementing Requiring support for the LCOFI bits listed above ensures that virtual LCOFIs can be delivered to an OS running in S-mode, and to a guest OS running in VS-mode. It is optional whether the LCOFI bit (bit 13) in each of |