zext.h

Zero-extend halfword

This instruction is defined by:

  • anyOf:

    • B, version >= 0

    • Zbb, version >= 0

This instruction is included in the following profiles:

  • RVA22S64 (Mandatory)

  • RVA22U64 (Mandatory)

Encoding

This instruction has different encodings in RV32 and RV64.
  • RV32

  • RV64

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Assembly format

zext.h rd, rs1

Synopsis

This instruction zero-extends the least-significant halfword of the source to XLEN by inserting 0’s into all of the bits more significant than 15.

The zext.h instruction is a pseudo-op for pack when Zbkb is implemented and XLEN == 32.
The zext.h instruction is a pseudo-op for packw when Zbkb is implemented and XLEN == 64.

Access

M HS U VS VU

Always

Always

Always

Always

Always

Decode Variables

  • RV32

  • RV64

Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];

Execution

  • IDL

  • Sail

if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
  raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
X[rd] = X[rs1][15:0];
{
  let rs1_val = X(rs1);
  let result : xlenbits = match op {
    RISCV_SEXTB => sign_extend(rs1_val[7..0]),
    RISCV_SEXTH => sign_extend(rs1_val[15..0]),
    RISCV_ZEXTH => zero_extend(rs1_val[15..0])
  };
  X(rd) = result;
  RETIRE_SUCCESS
}

Exceptions

This instruction may result in the following synchronous exceptions:

  • IllegalInstruction