vredxor.vs
No synopsis available.
This instruction is defined by:
-
V, version >= 0
This instruction is included in the following profiles:
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RVA22S64 (Optional)
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RVA22U64 (Optional)
Decode Variables
Bits<1> vm = $encoding[25];
Bits<5> vs2 = $encoding[24:20];
Bits<5> vs1 = $encoding[19:15];
Bits<5> vd = $encoding[11:7];
Execution
-
IDL
-
Sail
{
let SEW = get_sew();
let LMUL_pow = get_lmul_pow();
let num_elem_vs = get_num_elem(LMUL_pow, SEW);
let num_elem_vd = get_num_elem(0, SEW); /* vd regardless of LMUL setting */
if illegal_reduction() then { handle_illegal(); return RETIRE_FAIL };
if unsigned(vl) == 0 then return RETIRE_SUCCESS; /* if vl=0, no operation is performed */
let 'n = num_elem_vs;
let 'd = num_elem_vd;
let 'm = SEW;
let vm_val : vector('n, dec, bool) = read_vmask(num_elem_vs, vm, 0b00000);
let vd_val : vector('d, dec, bits('m)) = read_vreg(num_elem_vd, SEW, 0, vd);
let vs2_val : vector('n, dec, bits('m)) = read_vreg(num_elem_vs, SEW, LMUL_pow, vs2);
let mask : vector('n, dec, bool) = init_masked_source(num_elem_vs, LMUL_pow, vm_val);
sum : bits('m) = read_single_element(SEW, 0, vs1); /* vs1 regardless of LMUL setting */
foreach (i from 0 to (num_elem_vs - 1)) {
if mask[i] then {
sum = match funct6 {
MVV_VREDSUM => sum + vs2_val[i],
MVV_VREDAND => sum & vs2_val[i],
MVV_VREDOR => sum | vs2_val[i],
MVV_VREDXOR => sum ^ vs2_val[i],
MVV_VREDMIN => to_bits(SEW, min(signed(vs2_val[i]), signed(sum))),
MVV_VREDMINU => to_bits(SEW, min(unsigned(vs2_val[i]), unsigned(sum))),
MVV_VREDMAX => to_bits(SEW, max(signed(vs2_val[i]), signed(sum))),
MVV_VREDMAXU => to_bits(SEW, max(unsigned(vs2_val[i]), unsigned(sum)))
}
}
};
write_single_element(SEW, 0, vd, sum);
/* other elements in vd are treated as tail elements, currently remain unchanged */
/* TODO: configuration support for agnostic behavior */
vstart = zeros();
RETIRE_SUCCESS
}