andn
AND with inverted operand
This instruction is defined by:
-
anyOf:
-
B, version >= 0
-
Zbb, version >= 0
-
Zbkb, version >= 0
-
Zk, version >= 0
-
Zkn, version >= 0
-
Zks, version >= 0
-
This instruction is included in the following profiles:
-
RVA22S64 (Mandatory)
-
RVA22U64 (Mandatory)
Synopsis
This instruction must have data-independent timing when extension Zkt is enabled. |
This instruction performs the bitwise logical AND operation between rs1
and the
bitwise inversion of rs2
.
Decode Variables
Bits<5> rs2 = $encoding[24:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];
Execution
-
IDL
-
Sail
if (implemented?(ExtensionName::B) && (CSR[misa].B == 1'b0)) {
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
}
X[rd] = X[rs2] & ~X[rs1];
{
let rs1_val = X(rs1);
let rs2_val = X(rs2);
let result : xlenbits = match op {
RISCV_ANDN => rs1_val & ~(rs2_val),
RISCV_ORN => rs1_val | ~(rs2_val),
RISCV_XNOR => ~(rs1_val ^ rs2_val),
RISCV_MAX => to_bits(sizeof(xlen), max(signed(rs1_val), signed(rs2_val))),
RISCV_MAXU => to_bits(sizeof(xlen), max(unsigned(rs1_val), unsigned(rs2_val))),
RISCV_MIN => to_bits(sizeof(xlen), min(signed(rs1_val), signed(rs2_val))),
RISCV_MINU => to_bits(sizeof(xlen), min(unsigned(rs1_val), unsigned(rs2_val))),
RISCV_ROL => if sizeof(xlen) == 32
then rs1_val <<< rs2_val[4..0]
else rs1_val <<< rs2_val[5..0],
RISCV_ROR => if sizeof(xlen) == 32
then rs1_val >>> rs2_val[4..0]
else rs1_val >>> rs2_val[5..0]
};
X(rd) = result;
RETIRE_SUCCESS
}