mtvec

Machine Trap Vector Control

Controls where traps jump.

Attributes

Defining Extension

Sm, version >= 0

CSR Address

0x305

Length

32-bit

64-bit

Privilege Mode

Format

This CSR format changes dynamically.

Field Summary

Name Location Type Reset Value

Name	Location	Type	Reset Value
`BASE`	63:2	RW-R	0
`MODE`	1:0	RW-R	UNDEFINED_LEGAL

BASE

63:2

RW-R

MODE

1:0

RW-R

UNDEFINED_LEGAL

Fields

`BASE`

Location: 63:2
Description: Bits [MXLEN-1:2] of the exception vector physical address for any trap taken in M-mode.

The implementation physical memory map may resitrict which values are legal in this field.
Type: RW-R
Reset value: 0

`MODE`

Location: 1:0
Description: Vectoring mode for asynchronous interrupts.

0 - Direct, 1 - Vectored

When Direct, all synchronous exceptions and asynchronous interrupts jump to (mtvec.BASE << 2).

When Vectored, asynchronous interrupts jump to (mtvec.BASE << 2 + mcause*4) while synchronous exceptions continue to jump to (mtvec.BASE << 2).
Type: RW-R
Reset value: UNDEFINED_LEGAL

Software write

This CSR may store a value that is different from what software attempts to write.

When a software write occurs (e.g., through csrrw), the following determines the written value:

BASE = # Base spec says that BASE must be 4-byte aligned, which will always be the case
# implementations may put further constraints on BASE when MODE != Direct
# If that is the case, stvec should have an override for the implementation
return csr_value.BASE;

MODE = if (csr_value.MODE == 0) {
  if (ary_includes?<$array_size(MTVEC_MODES), 2>(MTVEC_MODES, 0)) {
    return csr_value.MODE;
  } else {
    return UNDEFINED_LEGAL_DETERMINISTIC;
  }
} else if (csr_value.MODE == 1) {
  if (ary_includes?<$array_size(MTVEC_MODES), 2>(MTVEC_MODES, 1)) {
    return csr_value.MODE;
  } else {
    return UNDEFINED_LEGAL_DETERMINISTIC;
  }
} else {
  return UNDEFINED_LEGAL_DETERMINISTIC;
}