vtype
Vector Type
Provides the default type used to interpret the contents of the vector register file.
Attributes
Requirement |
|||
|---|---|---|---|
Defining extensions |
|
||
CSR Address |
0xc21 |
||
Length |
* 32 when CSR[misa].MXL == 0 * 64 when CSR[misa].MXL == 1 |
||
Privilege Mode |
U |
Format
This CSR format changes dynamically.
Field Summary
| Name | Location | Type | Reset Value |
|---|---|---|---|
* 31 when CSR[mstatus].UXL == 0 * 63 when CSR[mstatus].UXL == 1 |
RO-H |
UNDEFINED_LEGAL |
|
7 |
RO-H |
UNDEFINED_LEGAL |
|
6 |
RO-H |
UNDEFINED_LEGAL |
|
5:3 |
RO-H |
UNDEFINED_LEGAL |
|
2:0 |
RO-H |
UNDEFINED_LEGAL |
Fields
VILL
- Location
-
-
31 when CSR[mstatus].UXL == 0
-
63 when CSR[mstatus].UXL == 1
-
- Description
-
The vill bit is used to encode that a previous vset{i}vl{i} instruction attempted to write an unsupported value to vtype.
| The vill bit is held in bit XLEN-1 of the CSR to support checking for illegal values with a branch on the sign bit. |
If the vill bit is set, then any attempt to execute a vector instruction that depends upon vtype will raise an illegal-instruction exception.
When the vill bit is set, the other XLEN-1 bits in vtype shall be zero.
It is recommended that at reset, vill is set.
- Type
-
RO-H
- Reset value
-
UNDEFINED_LEGAL
VMA
- Location
-
7
- Description
-
Vector mask agnostic bit. Modifies the behavior of destination inactive masked-off elements during the execution of vector instructions.
A value of 0 means inactive elements are undisturbed, meaning the corresponding set of destination elements in a vector register group retain the value they previously held.
A value of 1 means inactive elements are agnostic, meaning the corresponding set of destination elements in any vector destination operand can either retain the value they previously held, or are overwritten with 1s. Within a single vector instruction, each destination element can be either left undisturbed or overwritten with 1s, in any combination, and the pattern of undisturbed or overwritten with 1s is not required to be deterministic when the instruction is executed with the same inputs.
It is recommended that at reset, vill is set, and the remaining bits in vtype are zero.
- Type
-
RO-H
- Reset value
-
UNDEFINED_LEGAL
VTA
- Location
-
6
- Description
-
Vector tail agnostic bit. Modifies the bahavior of destination tail elements during the execution of vector instructions.
A value of 0 means tail elements are undisturbed, meaning the corresponding set of destination elements in a vector register group retain the value they previously held.
A value of 1 means tail elements are agnostic, meaning the corresponding set of destination elements in any vector destination operand can either retain the value they previously held, or are overwritten with 1s. Within a single vector instruction, each destination element can be either left undisturbed or overwritten with 1s, in any combination, and the pattern of undisturbed or overwritten with 1s is not required to be deterministic when the instruction is executed with the same inputs.
It is recommended that at reset, vill is set, and the remaining bits in vtype are zero.
- Type
-
RO-H
- Reset value
-
UNDEFINED_LEGAL
VSEW
- Location
-
5:3
- Description
-
The value in vsew sets the dynamic selected element width (SEW).
vsew[2:0] |
SEW |
Elements per vector register |
000 |
8 |
16 |
001 |
16 |
8 |
010 |
32 |
4 |
011 |
64 |
2 |
1XX |
Reserved |
Reserved |
It is recommended that at reset, vill is set, and the remaining bits in vtype are zero.
- Type
-
RO-H
- Reset value
-
UNDEFINED_LEGAL
VLMUL
- Location
-
2:0
- Description
-
Vector register group multiplier.
Multiple vector registers can be grouped together, so that a single vector instruction can operate on multiple vector registers. The term vector register group is used herein to refer to one or more vector registers used as a single operand to a vector instruction. Vector register groups can be used to provide greater execution efficiency for longer application vectors, but the main reason for their inclusion is to allow double-width or larger elements to be operated on with the same vector length as single-width elements. The vector length multiplier, LMUL, when greater than 1, represents the default number of vector registers that are combined to form a vector register group. Implementations must support LMUL integer values of 1, 2, 4, and 8.
| The vector architecture includes instructions that take multiple source and destination vector operands with different element widths, but the same number of elements. The effective LMUL (EMUL) of each vector operand is determined by the number of registers required to hold the elements. For example, for a widening add operation, such as add 32- bit values to produce 64-bit results, a double-width result requires twice the LMUL of the single-width inputs. |
LMUL can also be a fractional value, reducing the number of bits used in a single vector register. Fractional LMUL is used to increase the number of effective usable vector register groups when operating on mixed-width values.
It is recommended that at reset, vill is set, and the remaining bits in vtype are zero.
- Type
-
RO-H
- Reset value
-
UNDEFINED_LEGAL