mncause
Resumable NMI cause
The mncause CSR holds the reason for the NMI. If the reason is an interrupt, bit MXLEN-1 is set to 1, and the NMI cause is encoded in the least-significant bits. If the reason is an interrupt and NMI causes are not supported, bit MXLEN-1 is set to 1, and zero is written to the least-significant bits. If the reason is an exception within M-mode that results in a double trap as specified in the Smdbltrp extension, bit MXLEN-1 is set to 0 and the least-significant bits are set to the cause code corresponding to the exception that precipitated the double trap.
Attributes
Requirement |
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|---|---|---|---|
Defining extensions |
|
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CSR Address |
0x742 |
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Length |
* 32 when CSR[misa].MXL == 0 * 64 when CSR[misa].MXL == 1 |
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Privilege Mode |
M |
Format
This CSR format changes dynamically.
Field Summary
| Name | Location | Type | Reset Value |
|---|---|---|---|
* 31 when CSR[misa].MXL == 0 * 63 when CSR[misa].MXL == 1 |
RW-H |
UNDEFINED_LEGAL |
|
* 30:0 when CSR[misa].MXL == 0 * 62:0 when CSR[misa].MXL == 1 |
RW-H |
UNDEFINED_LEGAL |
Fields
INT
- Location
-
-
31 when CSR[misa].MXL == 0
-
63 when CSR[misa].MXL == 1
-
- Description
-
Written by hardware when a resumable NMI is taken into M-mode.
When set, the last non-maskable exception was caused by an asynchronous Interrupt.
If mcause is written with an undefined cause (combination of mcause.INT and mcause.CODE), an Illegal Instruction exception occurs.
If mcause is written with an undefined cause (combination of mcause.INT and mcause.CODE), neither mcause.INT nor mcause.CODE are modified.
- Type
-
RW-H
- Reset value
-
UNDEFINED_LEGAL