vxrm
Vector Fixed-Point Rounding Mode
Holds a 2-bit read-write rounding-mode field in the least-significant bits
Attributes
Requirement |
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|---|---|---|---|
Defining extensions |
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CSR Address |
0xa |
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Length |
* 32 when CSR[misa].MXL == 0 * 64 when CSR[misa].MXL == 1 |
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Privilege Mode |
U |
Format
This CSR format changes dynamically.
Field Summary
| Name | Location | Type | Reset Value |
|---|---|---|---|
* 31:0 when CSR[mstatus].UXL == 0 * 63:0 when CSR[mstatus].UXL == 1 |
RW-H |
UNDEFINED_LEGAL |
Fields
VALUE
- Location
-
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31:0 when CSR[mstatus].UXL == 0
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63:0 when CSR[mstatus].UXL == 1
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- Description
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The vector fixed-point rounding-mode register holds a two-bit read-write rounding-mode field in the least-significant bits (vxrm[1:0]). The upper bits, vxrm[XLEN-1:2], should be written as zeros. The vector fixed-point rounding-mode is given a separate CSR address to allow independent access, but is also reflected as a field in vcsr.
| A new rounding mode can be set while saving the original rounding mode using a single csrwi instruction. |
The fixed-point rounding algorithm is specified as follows. Suppose the pre-rounding result is v, and d bits of that result are to be rounded off. Then the rounded result is (v >> d) + r, where r depends on the rounding mode as specified in the following table of vxrm[1:0] values.
vxrm[1:0] |
Abbreviation |
Rounding Mode |
Rounding increment, r |
00 |
rnu |
round-to-nearest-up (add +0.5 LSB) |
v[d-1] |
01 |
rne |
round-to-nearest-even |
v[d-1] & (v[d-2:0]!=0 | v[d]) |
10 |
rdn |
round-down (truncate) |
0 |
11 |
rod |
round-to-odd (OR bits into LSB, aka "jam") |
!v[d] & v[d-1:0]!=0 Type:: RW-H Reset value:: UNDEFINED_LEGAL |
Software write
This CSR may store a value that is different from what software attempts to write.
When a software write occurs (e.g., through csrrw), the following determines the written value:
VALUE = return csr_value.VALUE & 3;