Implemented Extensions

The following are implemented by the generic_rv64 configuration:

  • A Atomic instructions

  • B Bitmanipulation instructions

  • C Compressed instructions

  • D Double-precision floating-point

  • F Single-precision floating-point

  • H Hypervisor

  • I Base integer ISA (RV32I or RV64I)

  • M Integer multiply and divide instructions

  • S Supervisor mode

  • Sm Machine mode

  • Smaia Advanced Interrupt Architecture, M-mode extension

  • Smcdeleg Performance counter delegation

  • Smcntrpmf Cycle and Instret Privilege Mode Filtering

  • Smhpm M-mode programmable hardware performance counters

  • Smpmp Physical Memory Protection

  • Ssaia Advanced Interrupt Architecture, S-mode extension

  • Ssccfg Supervisor-mode counter configuration

  • Sscofpmf Counter Overflow and Privilege Mode Filtering

  • Sstc Superivisor mode timer interrupts

  • Sv39 39-bit virtual address translation (3 level)

  • Sv48 48-bit virtual address translation (4 level)

  • U User-level privilege mode

  • V Variable-length vector

  • Zicbom Cache block management instructions

  • Zicboz Cache block zero instruction

  • Zicntr Architectural performance counters

  • Zicsr Control and status registers

  • Zihpm Programmable hardware performance counters

  • Zaamo Load-acquire/Store-release atomic instructions

  • Zalrsc Atomic read-modify-write instructions

  • Zba Address generation instructions

  • Zbb Basic bit manipulation

  • Zbs Single-bit instructions