mepc

Machine Exception Program Counter

Written with the PC of an instruction on an exception or interrupt taken in M-mode.

Also controls where the hart jumps on an exception return from M-mode.

Attributes

CSR Address

0x341

Defining extension

  • Sm, version >= 0

Length

64-bit

Privilege Mode

M

Format

mepc format
Figure 1. mepc format

Field Summary

Name Location Type Reset Value

PC

63:0

RW-RH

0

Fields

PC

Location

mepc[63:0]

Description

When a trap is taken into M-mode, mepc.PC is written with the virtual address of the instruction that was interrupted or that encountered the exception. Otherwise, mepc.PC is never written by the implementation, though it may be explicitly written by software.

On an exception retun from M-mode (from the MRET instruction), control transfers to the virtual address read out of mepc.PC.

Because PCs are always halfword-aligned, bit 0 of mepc.PC is always read-only 0.

Because PCs are always word-aligned, bits 1:0 of mepc.PC are always read-only 0.

When misa.C is clear, bit 1 is masked to zero. Writes to bit 1 are still captured, and may be visible on the next read with misa.C is set.

Type

RW-RH

Read-Write Restricted with Hardware update

Field is writeable by software. Only certain values are legal. Writing an illegal value into the field is ignored, such that the field retains its prior state. Hardware also updates the field without an explicit software write.)
Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

return csr_value.PC & ~64'b1;

Software read

This CSR may return a value that is different from what is stored in hardware.

  • Pruned

  • Original

return CSR[mepc].PC & ~64'b1;
if (implemented?(ExtensionName::C) && CSR[misa].C == 1'b1) {
  return CSR[mepc].PC & ~64'b1;
} else {
  return CSR[mepc].PC;
}