Sm Extension

Implemented Version

1.12.0

Versions

1.11.0
Ratification date

2019-12

Changes

  • Moved Machine spec to Ratified status.

  • Improvements to the description and commentary.

  • Specified which interrupt sources are reserved for standard use.

  • Allocated some synchronous exception causes for custom use.

  • Specified the priority ordering of synchronous exceptions.

  • Added specification that xRET instructions may, but are not required to, clear LR reservations if A extension present.

  • Made the mstatus.MPP field WARL, rather than WLRL.

  • Made the unused xip fields WPRI, rather than WIRI.

  • Made the unused misa fields WARL, rather than WIRI.

  • Rectified an editing error that misdescribed the mechanism by which mstatus is written upon an exception.

  • Described scheme for emulating misaligned AMOs.

  • Specified the behavior of the misa and xepc registers in systems with variable IALIGN.

  • Specified the behavior of writing self-contradictory values to the misa register.

  • Specified contents of CSRs across XLEN modification.

  • Moved PLIC chapter into its own document.

1.12.0
Ratification date

2021-12

Changes

  • Changed MRET to clear mstatus.MPRV when leaving M-mode.

  • Relaxed I/O regions have been specified to follow RVWMO. The previous specification implied that PPO rules other than fences and acquire/release annotations did not apply.

  • Constrained the LR/SC reservation set size and shape when using page-based virtual memory.

  • PMP changes require an SFENCE.VMA on any hart that implements page-based virtual memory, even if VM is not currently enabled.

  • Removed the N extension.

  • Defined the mandatory RV32-only CSR mstatush, which contains most of the same fields as the upper 32 bits of RV64’s mstatus.

  • Defined the mandatory CSR mconfigptr, which if nonzero contains the address of a configuration data structure.

  • Defined optional mseccfg and mseccfgh CSRs, which control the machine’s security configuration.

  • Defined menvcfg CSR (and RV32-only menvcfgh), which control various characteristics of the execution environment.

  • Designated part of SYSTEM major opcode for custom use.

  • Permitted the unconditional delegation of less-privileged interrupts.

  • Added optional big-endian and bi-endian support.

  • Made priority of load/store/AMO address-misaligned exceptions implementation-defined relative to load/store/AMO page-fault and access-fault exceptions.

  • Software breakpoint exceptions are permitted to write either 0 or the pc to xtval.

  • Specified relaxed constraints for implicit reads of non-idempotent regions.

1.13.0
Ratification date

2023-12

Changes

  • Redefined misa.MXL to be read-only, making MXLEN a constant.

  • Defined the misa.B field to reflect that the B extension has been implemented.

  • Defined the misa.V field to reflect that the V extension has been implemented.

  • Defined the RV32-only medelegh CSR.

  • Defined the misaligned atomicity granule PMA, superseding the proposed Zam extension.

  • Defined hardware error and software check exception codes.

  • Specified synchronization requirements when changing the PBMTE fields in menvcfg and henvcfg.

  • Exposed count-overflow interrupts to VS-mode via the Shlcofideleg extension.

  • Relaxed behavior of some HINTs when MXLEN > XLEN.

  • Transliterated the document from LaTeX into AsciiDoc.

  • Included all ratified extensions through March 2024.

  • Clarified that "platform- or custom-use" interrupts are actually "platform-use interrupts", where the platform can choose to make some custom.

  • Clarified semantics of explicit accesses to CSRs wider than XLEN bits.

  • Clarified that MXLEN≥SXLEN.

  • Clarified that WFI is not a HINT instruction.

  • Clarified that, for a given exception cause, xtval might sometimes be set to a nonzero value but sometimes not.

  • Clarified exception behavior of unimplemented or inaccessible CSRs.

  • Replaced the concept of vacant memory regions with inaccessible memory or I/O regions.

  • Clarified that timer and count-overflow interrupts' arrival in interrupt-pending registers is not immediate.

  • Clarified that MXR affects only explicit memory accesses.

Synopsis

This chapter describes the machine-level operations available in machine-mode (M-mode), which is the highest privilege mode in a RISC-V hart. M-mode is used for low-level access to a hardware platform and is the first mode entered at reset. M-mode can also be used to implement features that are too difficult or expensive to implement in hardware directly. The RISC-V machine-level ISA contains a common core that is extended depending on which other privilege levels are supported and other details of the hardware implementation. This chapter describes the RISC-V machine-level architecture, which contains a common core that is used with various supervisor-level address translation and protection schemes.

Instructions

The following instructions are added by this extension in the generic_rv64 configuration:

mret

Machine Exception Return

wfi

Wait for interrupt

Parameters

This extension has the following implementation options:

ARCH_ID

Vendor-specific architecture ID in marchid

CONFIG_PTR_ADDRESS

Physical address of the unified discovery configuration data structure. This address is reported in the mconfigptr CSR.

IMP_ID

Vendor-specific implementation ID in mimpid

MISALIGNED_LDST

Does the implementation perform non-atomic misaligned loads and stores to main memory (does not affect misaligned support to device memory)? If not, the implementation always throws a misaligned exception.

MISALIGNED_LDST_EXCEPTION_PRIORITY

The relative priority of a load/store/AMO exception vs. load/store/AMO page-fault or access-fault exceptions.

May be one of:

low

Misaligned load/store/AMO exceptions are always lower priority than load/store/AMO page-fault and access-fault exceptions.

high

Misaligned load/store/AMO exceptions are always higher priority than load/store/AMO page-fault and access-fault exceptions.

MISALIGNED_LDST_EXCEPTION_PRIORITY cannot be "high" when MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is non-zero, since the atomicity of an access cannot be determined in that case until after address translation.

MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE

The maximum granule size, in bytes, that the hart can atomically perform a misaligned load/store/AMO without raising a Misaligned exception. When MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is 0, the hart cannot atomically perform a misaligned load/store/AMO. When a power of two, the hart can atomically load/store/AMO a misaligned access that is fully contained in a MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE-aligned region.

Even if the hart is capable of performing a misaligned load/store/AMO atomically, a misaligned exception may still occur if the access does not have the appropriate Misaligned Atomicity Granule PMA set.
MISALIGNED_SPLIT_STRATEGY

When misaligned accesses are supported, this determines the order in the implementation appears to process the load/store, which determines how/which exceptions will be reported

Options:

  • by_byte: The load/store appears to be broken into byte-sized accesses that processed sequentially from smallest address to largest address

  • custom: Something else. Will result in a call to unpredictable() in the execution

MISA_CSR_IMPLEMENTED

Whether or not the misa CSR returns zero or a non-zero value.

Possible values:

true

The misa CSR returns a non-zero value.

false

The misa CSR is read-only-0.

MTVAL_WIDTH

The number of implemented bits in the mtval CSR. This is the CSR that may be written when a trap is taken into M-mode with exception-specific information to assist software in handling the trap (e.g., address associated with exception).

Must be greater than or equal to max(PHYS_ADDR_WIDTH, VA_SIZE)

MTVEC_BASE_ALIGNMENT_DIRECT

Byte alignment for mtvec.BASE when mtvec.MODE is Direct.

Cannot be less than 4-byte alignment.

MTVEC_BASE_ALIGNMENT_VECTORED

Byte alignment for mtvec.BASE when mtvec.MODE is Vectored.

Cannot be less than 4-byte alignment.

MTVEC_MODES

Modes supported by mtvec.MODE. If only one, it is assumed to be read-only with that value.

M_MODE_ENDIANESS

Endianess of data in M-mode. Can be one of:

little

M-mode data is always little endian

big

M-mode data is always big endian

dynamic

M-mode data can be either little or big endian, depending on the CSR field mstatus.MBE
PHYS_ADDR_WIDTH

Number of bits in the physical address space.

PMA_GRANULARITY

log2 of the smallest supported PMA region.

Generally, for systems with an MMU, should not be smaller than 12, as that would preclude caching PMP results in the TLB along with virtual memory translations

PRECISE_SYNCHRONOUS_EXCEPTIONS

Whether or not all synchronous exceptions are precise.

If false, any exception not otherwise mandated to precise (e.g., PMP violation) will cause execution to enter an unpredictable state.

REPORT_ENCODING_IN_MTVAL_ON_ILLEGAL_INSTRUCTION

When true, mtval is written with the encoding of an instruction that causes an IllegalInstruction exception.

When false mtval is written with 0 when an IllegalInstruction exception occurs.

REPORT_VA_IN_MTVAL_ON_BREAKPOINT

When true, mtval is written with the virtual PC of the EBREAK instruction (same information as mepc).

When false, mtval is written with 0 on an EBREAK instruction.

Regardless, mtval is always written with a virtual PC when an external breakpoint is generated

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_ACCESS_FAULT

When true, mtval is written with the virtual PC of an instructino when fetch causes an InstructionAccessFault.

WHen false, mtval is written with 0 when an instruction fetch causes an InstructionAccessFault.

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_MISALIGNED

When true, mtval is written with the virtual PC when an instruction fetch is misaligned.

When false, mtval is written with 0 when an instruction fetch is misaligned.

Note that when IALIGN=16 (i.e., when the C or one of the Zc* extensions are implemented), it is impossible to generate a misaligned fetch, and so this parameter has no effect.

REPORT_VA_IN_MTVAL_ON_INSTRUCTION_PAGE_FAULT

When true, mtval is written with the virtual PC of an instructino when fetch causes an InstructionPageFault.

WHen false, mtval is written with 0 when an instruction fetch causes an InstructionPageFault.

REPORT_VA_IN_MTVAL_ON_LOAD_ACCESS_FAULT

When true, mtval is written with the virtual address of a load when it causes a LoadAccessFault.

WHen false, mtval is written with 0 when a load causes a LoadAccessFault.

REPORT_VA_IN_MTVAL_ON_LOAD_MISALIGNED

When true, mtval is written with the virtual address of a load instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, mtval is written with 0 when a load address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_MTVAL_ON_LOAD_PAGE_FAULT

When true, mtval is written with the virtual address of a load when it causes a LoadPageFault.

WHen false, mtval is written with 0 when a load causes a LoadPageFault.

REPORT_VA_IN_MTVAL_ON_STORE_AMO_ACCESS_FAULT

When true, mtval is written with the virtual address of a store when it causes a StoreAmoAccessFault.

WHen false, mtval is written with 0 when a store causes a StoreAmoAccessFault.

REPORT_VA_IN_MTVAL_ON_STORE_AMO_MISALIGNED

When true, mtval is written with the virtual address of a store instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, mtval is written with 0 when a store address is misaligned and MISALIGNED_LDST is false.

REPORT_VA_IN_MTVAL_ON_STORE_AMO_PAGE_FAULT

When true, mtval is written with the virtual address of a store when it causes a StoreAmoPageFault.

WHen false, mtval is written with 0 when a store causes a StoreAmoPageFault.

TRAP_ON_EBREAK

Whether or not an EBREAK causes a synchronous exception.

The spec states that implementations may handle EBREAKs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ECALL_FROM_M

Whether or not an ECALL-from-M-mode causes a synchronous exception.

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

TRAP_ON_ILLEGAL_WLRL

When true, writing an illegal value to a WLRL CSR field raises an IllegalInstruction exception.

When false, writing an illegal value to a WLRL CSR field is unpredictable.

TRAP_ON_RESERVED_INSTRUCTION

When true, fetching an unimplemented and/or undefined instruction from the standard/reserved encoding space will cause an IllegalInstruction exception.

When false, fetching such an instruction is UNPREDICTABLE.

TRAP_ON_UNIMPLEMENTED_CSR

When true, accessing an unimplemented CSR (via a Zicsr instruction) will cause an IllegalInstruction exception.

When false, accessing an unimplemented CSR (via a Zicsr instruction) is unpredictable.

TRAP_ON_UNIMPLEMENTED_INSTRUCTION

When true, fetching an unimplemented instruction from the custom encoding space will cause an IllegalInstruction exception.

When false, fetching an unimplemented instruction is UNPREDICTABLE.

VENDOR_ID_BANK

JEDEC Vendor ID bank, for mvendorid

VENDOR_ID_OFFSET

Vendor JEDEC code offset, for mvendorid

XLEN

XLEN in M-mode (AKA MXLEN, tracked by issue #52)