mhpmcounter10

Machine Hardware Performance Counter 10

Programmable hardware performance counter.

Attributes

CSR Address	0xb0a
Defining extension	Smhpm, version >= 0
Length	64-bit
Privilege Mode	M

CSR Address

0xb0a

Defining extension

Smhpm, version >= 0

Length

64-bit

Privilege Mode

Format

Figure 1. mhpmcounter10 format

Field Summary

Name Location Type Reset Value

Name	Location	Type	Reset Value
`COUNT`	63:0	RW-H	UNDEFINED_LEGAL

COUNT

63:0

RW-H

UNDEFINED_LEGAL

Fields

`COUNT`

Location: mhpmcounter10[63:0]
Description

Performance counter for event selected in mhpmevent10.EVENT.

+ Increments every time event occurs unless:

+ * mcountinhibit.HPM10 or its alias scountinhibit.HPM10 is set * mhpmevent10.MINH is set and the current privilege level is M * mhpmevent10.SINH or its alias hpmevent10..SINH is set and the current privilege level is (H)S * mhpmevent10.UINH or its alias hpmevent10.SINH is set and the current privilege level is U * mhpmevent10.VSINH or its alias hpmevent10.SINH is set and the current privilege level is VS * mhpmevent10.VUINH or its alias hpmevent10.SINH is set and the current privilege level is VU

Unimplemented performance counter. Must be read-only 0 (access does not cause trap).

Type

RW-H	Read-Write with Hardware update Field is writable by software. Any value that fits in the field is acceptable. Hardware also updates the field without an explicit software write.

Reset value: UNDEFINED_LEGAL

Software read

This CSR may return a value that is different from what is stored in hardware.

Pruned
Original

return read_hpm_counter(10);

if (HPM_COUNTER_EN[10]) {
  return read_hpm_counter(10);
} else {
  return 0;
}