Smhpm Extension

Versions

1.11.0

Ratification date

2019-12

Changes

Defined the mcountinhibit CSR, which stops performance counters from incrementing to reduce energy consumption.

1.12.0

Ratification date

2021-12

Changes

PMP changes require an SFENCE.VMA on any hart that implements page-based virtual memory, even if VM is not currently enabled.
PMP reset values are now platform-defined.
An additional 48 optional PMP registers have been defined.

1.13.0

M-mode programmable hardware performance counters

This extension has the following implementation options:

COUNTINHIBIT_EN: Indicates which hardware performance monitor counters can be disabled from mcountinhibit.

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set COUNTINHIBIT_EN[3] to true.

COUNTINHIBIT_EN[1] can never be true, since it corresponds to mcountinhibit, which is always read-only-0.

COUNTINHIBIT_EN[3:31] must all be false if Zihpm is not implemented.
HPM_COUNTER_EN: List of HPM counters that are enabled. There is one entry for each hpmcounter.

The first three entries must be false (as they correspond to CY, IR, TM in, e.g. mhmpcountinhibit) Index 3 in HPM_COUNTER_EN corresponds to hpmcounter3. Index 31 in HPM_COUNTER_EN corresponds to hpmcounter31.
HPM_EVENTS: List of defined event numbers that can be written into hpmeventN
MCOUNTENABLE_EN: Indicates which counters can be delegated via mcounteren.

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set MCOUNTENABLE_EN[3] to true.

MCOUNTENABLE_EN[0:2] must all be false if Zicntr is not implemented. MCOUNTENABLE_EN[3:31] must all be false if Zihpm is not implemented.