srlw

Shift right logical word

This instruction is defined by:

Encoding

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Synopsis

Logical shift the 32-bit value in rs1 right by the value in the lower 5 bits of rs2, and store the sign-extended result in rd.

Access

M

HS

U

VS

VU

Always

Always

Always

Always

Always

Decode Variables

Bits<5> rs2 = $encoding[24:20];
Bits<5> rs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];

Execution

  • Pruned, XLEN == 64

  • Original

X[rd] = sext(X[rs1][31:0] >> X[rs2][4:0], 31);
X[rd] = sext(X[rs1][31:0] >> X[rs2][4:0], 31);