mhpmcounter27

Machine Hardware Performance Counter 27

Programmable hardware performance counter.

Attributes

CSR Address	0xb1b
Defining extension	Smhpm, version >= 0
Length	64-bit
Privilege Mode	M

CSR Address

0xb1b

Defining extension

Smhpm, version >= 0

Length

64-bit

Privilege Mode

Format

Figure 1. mhpmcounter27 format

Field Summary

Name Location Type Reset Value

Name	Location	Type	Reset Value
`COUNT`	63:0	RO	0

COUNT

63:0

Fields

`COUNT`

Location: mhpmcounter27[63:0]
Description

Performance counter for event selected in mhpmevent27.EVENT.

+ Increments every time event occurs unless:

+ * mcountinhibit.HPM27 or its alias scountinhibit.HPM27 is set * mhpmevent27.MINH is set and the current privilege level is M * mhpmevent27.SINH or its alias hpmevent27..SINH is set and the current privilege level is (H)S * mhpmevent27.UINH or its alias hpmevent27.SINH is set and the current privilege level is U * mhpmevent27.VSINH or its alias hpmevent27.SINH is set and the current privilege level is VS * mhpmevent27.VUINH or its alias hpmevent27.SINH is set and the current privilege level is VU

Unimplemented performance counter. Must be read-only 0 (access does not cause trap).

Type

RO	Read-Only Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value: 0

Software read

This CSR may return a value that is different from what is stored in hardware.

Pruned
Original

return 0;

if (HPM_COUNTER_EN[27]) {
  return read_hpm_counter(27);
} else {
  return 0;
}