mhpmcounter28

Machine Hardware Performance Counter 28

Programmable hardware performance counter.

Attributes

CSR Address

0xb1c

Defining extension

  • Smhpm, version >= 0

Length

64-bit

Privilege Mode

M

Format

mhpmcounter28 format
Figure 1. mhpmcounter28 format

Field Summary

Name Location Type Reset Value

COUNT

63:0

RO

0

Fields

COUNT

Location

mhpmcounter28[63:0]

Description

Performance counter for event selected in mhpmevent28.EVENT.

+ Increments every time event occurs unless:

+ * mcountinhibit.HPM28 or its alias scountinhibit.HPM28 is set * mhpmevent28.MINH is set and the current privilege level is M * mhpmevent28.SINH or its alias hpmevent28..SINH is set and the current privilege level is (H)S * mhpmevent28.UINH or its alias hpmevent28.SINH is set and the current privilege level is U * mhpmevent28.VSINH or its alias hpmevent28.SINH is set and the current privilege level is VS * mhpmevent28.VUINH or its alias hpmevent28.SINH is set and the current privilege level is VU

+

Unimplemented performance counter. Must be read-only 0 (access does not cause trap).

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

Software read

This CSR may return a value that is different from what is stored in hardware.

  • Pruned

  • Original

return 0;
if (HPM_COUNTER_EN[28]) {
  return read_hpm_counter(28);
} else {
  return 0;
}