Configuration of generic_rv64

Vendor-specific architecture ID in marchid

Sm

Number of implemented ASID bits. Maximum is 16 for XLEN==64, and 9 for XLEN==32

S

The observable size of a cache block, in bytes

Zicbom, Zicboz, Zicbop

The observable size of a cache block, in bytes

Zicbop, Zicboz, Zicbom

The observable size of a cache block, in bytes

Zicboz, Zicbom, Zicbop

Physical address of the unified discovery configuration data structure. This address is reported in the mconfigptr CSR.

Sm

Indicates which hardware performance monitor counters can be disabled from mcountinhibit.

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set COUNTINHIBIT_EN[3] to true.

COUNTINHIBIT_EN[1] can never be true, since it corresponds to mcountinhibit, which is always read-only-0.

COUNTINHIBIT_EN[3:31] must all be false if Zihpm is not implemented.

Smhpm

When true, an implementation prohibits setting menvcfg.CBIE == 11 such that all cbo.inval instructions either trap (when menvcfg.CBIE == '00') or flush (when menvcfg.CBIE == '01').

When false, an implementation allows a true INVAL operation for cbo.inval, and thus supports the setting menvcfg.CBIE == 11.

Zicbom

Whether or not writing mode=Bare is supported in the hgatp register.

H

Indicates which counters can delegated via hcounteren

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set HCOUNTENABLE_EN[3] to true.

HCOUNTENABLE_EN[0:2] must all be false if Zicntr is not implemented. HCOUNTENABLE_EN[3:31] must all be false if Zihpm is not implemented.

H

List of HPM counters that are enabled. There is one entry for each hpmcounter.

The first three entries must be false (as they correspond to CY, IR, TM in, e.g. mhmpcountinhibit) Index 3 in HPM_COUNTER_EN corresponds to hpmcounter3. Index 31 in HPM_COUNTER_EN corresponds to hpmcounter31.

Smhpm

List of defined event numbers that can be written into hpmeventN

Smhpm

Indicates whether or not hardware will write to mstatus.FS

Values are:

F

Indicates whether or not hardware will write to mstatus.VS

Values are:

V

Whether writes from M-mode, U-mode, or S-mode to vsatp with an illegal mode setting are ignored (as they are with satp), or if they are treated as WARL, leading to undpredictable behavior.

H

Vendor-specific implementation ID in mimpid

Sm

Whether or not a Store Conditional fails if its physical address and size do not exactly match the physical address and size of the last Load Reserved in program order (independent of whether or not the SC is in the current reservation set)

A

Whether or not an sc.l/sc.d will fail if its VA does not match the VA of the prior lr.l/lr.d, even if the physical address of the SC and LR are the same

A

What to do when an LR/SC address is misaligned and MISALIGNED_AMO == false.

A

Strategy used to handle reservation sets.

A

Indicates which counters can be delegated via mcounteren.

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set MCOUNTENABLE_EN[3] to true.

MCOUNTENABLE_EN[0:2] must all be false if Zicntr is not implemented. MCOUNTENABLE_EN[3:31] must all be false if Zihpm is not implemented.

Smhpm

whether or not the implementation supports misaligned atomics in main memory

A

Does the implementation perform non-atomic misaligned loads and stores to main memory (does not affect misaligned support to device memory)? If not, the implementation always throws a misaligned exception.

Sm

The relative priority of a load/store/AMO exception vs. load/store/AMO page-fault or access-fault exceptions.

May be one of:

MISALIGNED_LDST_EXCEPTION_PRIORITY cannot be "high" when MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is non-zero, since the atomicity of an access cannot be determined in that case until after address translation.

Sm

The maximum granule size, in bytes, that the hart can atomically perform a misaligned load/store/AMO without raising a Misaligned exception. When MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE is 0, the hart cannot atomically perform a misaligned load/store/AMO. When a power of two, the hart can atomically load/store/AMO a misaligned access that is fully contained in a MISALIGNED_MAX_ATOMICITY_GRANULE_SIZE-aligned region.

Sm

When misaligned accesses are supported, this determines the order in the implementation appears to process the load/store, which determines how/which exceptions will be reported

Options:

Sm

Whether or not the misa CSR returns zero or a non-zero value.

Possible values:

Sm

The set of values that mstatus.FS will accept from a software write.

F, S

The set of values that mstatus.FS will accept from a software write.

S, F

When S is enabled but F is not, mstatus.FS is optionally writeable.

This parameter only has an effect when both S and F mode are disabled.

S

Whether or not mstatus.TVM is implemented.

When not implemented mstatus.TVM will be read-only-zero.

S

The set of values that mstatus.VS will accept from a software write.

S, V

The set of values that mstatus.VS will accept from a software write.

V, S

When S is enabled but V is not, mstatus.VS is optionally writeable.

This parameter only has an effect when both S and V mode are disabled.

S

The number of implemented bits in the mtval CSR. This is the CSR that may be written when a trap is taken into M-mode with exception-specific information to assist software in handling the trap (e.g., address associated with exception).

Must be greater than or equal to max(PHYS_ADDR_WIDTH, VA_SIZE)

Sm

Byte alignment for mtvec.BASE when mtvec.MODE is Direct.

Cannot be less than 4-byte alignment.

Sm

Byte alignment for mtvec.BASE when mtvec.MODE is Vectored.

Cannot be less than 4-byte alignment.

Sm

Modes supported by mtvec.MODE. If only one, it is assumed to be read-only with that value.

Sm

When the A extensions is supported, indicates whether or not the extension can be disabled in the misa.A bit.

A

Indicates whether or not the B extension can be disabled with the misa.B bit.

B

Indicates whether or not the C extension can be disabled with the misa.C bit.

C

Indicates whether or not the D extension can be disabled with the misa.D bit.

D

Indicates whether or not the F extension can be disabled with the misa.F bit.

F

Indicates whether or not the H extension can be disabled with the misa.H bit.

H

Indicates whether or not the M extension can be disabled with the misa.M bit.

M

Indicates whether or not the S extension can be disabled with the misa.S bit.

S

Indicates whether or not the U extension can be disabled with the misa.U bit.

U

Indicates whether or not the V extension can be disabled with the misa.V bit.

V

Endianess of data in M-mode. Can be one of:

Sm

Number of supported virtualized guest interrupts

Corresponds to the GEILEN parameter in the RVI specs

H

Number of implemented PMP entries. Can be any value between 0-64, inclusive.

The architecture mandates that the number of implemented PMP registers must appear to be 0, 16, or 64.

Therefore, pmp registers will behave as follows according to NUN_PMP_ENTRIES:

When NUM_PMP_ENTRIES is not exactly 0, 16, or 64, some extant pmp registers, and associated pmpNcfg, will be read-only zero (but will never cause an exception).

Smpmp

Number of bits in the physical address space.

Sm

log2 of the smallest supported PMA region.

Generally, for systems with an MMU, should not be smaller than 12, as that would preclude caching PMP results in the TLB along with virtual memory translations

Sm

log2 of the smallest supported PMP region.

Generally, for systems with an MMU, should not be smaller than 12, as that would preclude caching PMP results in the TLB along with virtual memory translations

Note that PMP_GRANULARITY is equal to G+2 (not G) as described in the privileged architecture.

Smpmp

Whether or not all synchronous exceptions are precise.

If false, any exception not otherwise mandated to precise (e.g., PMP violation) will cause execution to enter an unpredictable state.

Sm

When true, mtval is written with the encoding of an instruction that causes an IllegalInstruction exception.

When false mtval is written with 0 when an IllegalInstruction exception occurs.

Sm

When true, stval is written with the encoding of an instruction that causes an IllegalInstruction exception.

When false stval is written with 0 when an IllegalInstruction exception occurs.

S

When true, vstval is written with the encoding of an instruction that causes an IllegalInstruction exception.

When false vstval is written with 0 when an IllegalInstruction exception occurs.

H

Whether or not GPA >> 2 is written into htval/mtval2 when an instruction guest page fault occurs.

If false, 0 will be written into htval/mtval2 on an instruction guest page fault.

H

Whether or not GPA >> 2 is written into htval/mtval2 when a guest page fault occurs while walking a VS-mode page table.

If false, 0 will be written into htval/mtval2 on an intermediate guest page fault.

H

Whether or not GPA >> 2 is written into htval/mtval2 when a load guest page fault occurs.

If false, 0 will be written into htval/mtval2 on a load guest page fault.

H

Whether or not GPA >> 2 is written into htval/mtval2 when a store/amo guest page fault occurs.

If false, 0 will be written into htval/mtval2 on a store/amo guest page fault.

H

When true, mtval is written with the virtual PC of the EBREAK instruction (same information as mepc).

When false, mtval is written with 0 on an EBREAK instruction.

Regardless, mtval is always written with a virtual PC when an external breakpoint is generated

Sm

When true, mtval is written with the virtual PC of an instructino when fetch causes an InstructionAccessFault.

WHen false, mtval is written with 0 when an instruction fetch causes an InstructionAccessFault.

Sm

When true, mtval is written with the virtual PC when an instruction fetch is misaligned.

When false, mtval is written with 0 when an instruction fetch is misaligned.

Note that when IALIGN=16 (i.e., when the C or one of the Zc* extensions are implemented), it is impossible to generate a misaligned fetch, and so this parameter has no effect.

Sm

When true, mtval is written with the virtual PC of an instructino when fetch causes an InstructionPageFault.

WHen false, mtval is written with 0 when an instruction fetch causes an InstructionPageFault.

Sm

When true, mtval is written with the virtual address of a load when it causes a LoadAccessFault.

WHen false, mtval is written with 0 when a load causes a LoadAccessFault.

Sm

When true, mtval is written with the virtual address of a load instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, mtval is written with 0 when a load address is misaligned and MISALIGNED_LDST is false.

Sm

When true, mtval is written with the virtual address of a load when it causes a LoadPageFault.

WHen false, mtval is written with 0 when a load causes a LoadPageFault.

Sm

When true, mtval is written with the virtual address of a store when it causes a StoreAmoAccessFault.

WHen false, mtval is written with 0 when a store causes a StoreAmoAccessFault.

Sm

When true, mtval is written with the virtual address of a store instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, mtval is written with 0 when a store address is misaligned and MISALIGNED_LDST is false.

Sm

When true, mtval is written with the virtual address of a store when it causes a StoreAmoPageFault.

WHen false, mtval is written with 0 when a store causes a StoreAmoPageFault.

Sm

When true, stval is written with the virtual PC of the EBREAK instruction (same information as mepc).

When false, stval is written with 0 on an EBREAK instruction.

Regardless, stval is always written with a virtual PC when an external breakpoint is generated

S

When true, stval is written with the virtual PC of an instructino when fetch causes an InstructionAccessFault.

WHen false, stval is written with 0 when an instruction fetch causes an InstructionAccessFault.

S

When true, stval is written with the virtual PC when an instruction fetch is misaligned.

When false, stval is written with 0 when an instruction fetch is misaligned.

Note that when IALIGN=16 (i.e., when the C or one of the Zc* extensions are implemented), it is impossible to generate a misaligned fetch, and so this parameter has no effect.

S

When true, stval is written with the virtual PC of an instructino when fetch causes an InstructionPageFault.

WHen false, stval is written with 0 when an instruction fetch causes an InstructionPageFault.

S

When true, stval is written with the virtual address of a load when it causes a LoadAccessFault.

WHen false, stval is written with 0 when a load causes a LoadAccessFault.

S

When true, stval is written with the virtual address of a load instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, stval is written with 0 when a load address is misaligned and MISALIGNED_LDST is false.

S

When true, stval is written with the virtual address of a load when it causes a LoadPageFault.

WHen false, stval is written with 0 when a load causes a LoadPageFault.

S

When true, stval is written with the virtual address of a store when it causes a StoreAmoAccessFault.

WHen false, stval is written with 0 when a store causes a StoreAmoAccessFault.

S

When true, stval is written with the virtual address of a store instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, stval is written with 0 when a store address is misaligned and MISALIGNED_LDST is false.

S

When true, stval is written with the virtual address of a store when it causes a StoreAmoPageFault.

WHen false, stval is written with 0 when a store causes a StoreAmoPageFault.

S

When true, vstval is written with the virtual PC of the EBREAK instruction (same information as mepc).

When false, vstval is written with 0 on an EBREAK instruction.

Regardless, vstval is always written with a virtual PC when an external breakpoint is generated

H

When true, vstval is written with the virtual PC of an instructino when fetch causes an InstructionAccessFault.

WHen false, vstval is written with 0 when an instruction fetch causes an InstructionAccessFault.

H

When true, vstval is written with the virtual PC when an instruction fetch is misaligned.

When false, vstval is written with 0 when an instruction fetch is misaligned.

Note that when IALIGN=16 (i.e., when the C or one of the Zc* extensions are implemented), it is impossible to generate a misaligned fetch, and so this parameter has no effect.

H

When true, vstval is written with the virtual PC of an instructino when fetch causes an InstructionPageFault.

WHen false, vstval is written with 0 when an instruction fetch causes an InstructionPageFault.

H

When true, vstval is written with the virtual address of a load when it causes a LoadAccessFault.

WHen false, vstval is written with 0 when a load causes a LoadAccessFault.

H

When true, vstval is written with the virtual address of a load instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, vstval is written with 0 when a load address is misaligned and MISALIGNED_LDST is false.

H

When true, vstval is written with the virtual address of a load when it causes a LoadPageFault.

WHen false, vstval is written with 0 when a load causes a LoadPageFault.

H

When true, vstval is written with the virtual address of a store when it causes a StoreAmoAccessFault.

WHen false, vstval is written with 0 when a store causes a StoreAmoAccessFault.

H

When true, vstval is written with the virtual address of a store instruction when the address is misaligned and MISALIGNED_LDST is false.

When false, vstval is written with 0 when a store address is misaligned and MISALIGNED_LDST is false.

H

When true, vstval is written with the virtual address of a store when it causes a StoreAmoPageFault.

WHen false, vstval is written with 0 when a store causes a StoreAmoPageFault.

H

Whether or not satp.MODE == Bare is supported.

S

Indicates which counters can delegated via scounteren

An unimplemented counter cannot be specified, i.e., if HPM_COUNTER_EN[3] is false, it would be illegal to set SCOUNTENABLE_EN[3] to true.

SCOUNTENABLE_EN[0:2] must all be false if Zicntr is not implemented. SCOUNTENABLE_EN[3:31] must all be false if Zihpm is not implemented.

S

The number of implemented bits in stval.

Must be greater than or equal to max(PHYS_ADDR_WIDTH, VA_SIZE)

S

Whether or not stvec.MODE supports Direct (0).

S

Whether or not stvec.MODE supports Vectored (1).

S

Whether or not Sv32x4 translation mode is supported.

H

Whether or not Sv32 translation is supported in first-stage (VS-stage) translation.

H

Whether or not Sv39x4 translation mode is supported.

H

Whether or not Sv39 translation is supported in first-stage (VS-stage) translation.

H

Whether or not Sv48x4 translation mode is supported.

H

Whether or not Sv48 translation is supported in first-stage (VS-stage) translation.

H

Whether or not Sv57x4 translation mode is supported.

H

Whether or not Sv57 translation is supported in first-stage (VS-stage) translation.

H

Whether or not writing mode=Bare is supported in the satp register.

S

Set of XLENs supported in S-mode. Can be one of:

S

Endianess of data in S-mode. Can be one of:

S

Whether or not a real hardware time CSR exists. Implementations can either provide a real CSR or emulate access at M-mode.

Possible values:

Zicntr

Value written into htinst/mtinst on a Breakpoint exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE

H

Value to write into htval/mtval2 when there is a guest page fault on a final translation.

Possible values: * "always zero": Always write the value zero * "always pseudoinstruction": Always write the pseudoinstruction

H

Value to write into htval/mtval2 when there is a guest page fault on a final translation.

Possible values: * "always zero": Always write the value zero * "always pseudoinstruction": Always write the pseudoinstruction * "always transformed standard instruction": Always write the transformation of the standard instruction encoding * "custom": A custom value, which will cause an UNPREDICTABLE event.

H

Value to write into htval/mtval2 when there is a guest page fault on a final translation.

Possible values: * "always zero": Always write the value zero * "always pseudoinstruction": Always write the pseudoinstruction * "always transformed standard instruction": Always write the transformation of the standard instruction encoding * "custom": A custom value, which will cause an UNPREDICTABLE event.

H

Value written into htinst/mtinst when there is an instruction address misaligned exception.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE

H

Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which resuls in UNPREDICTABLE

H

Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which resuls in UNPREDICTABLE

H

Value written into htinst/mtinst on a LoadPageFault exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which resuls in UNPREDICTABLE

H

Value written into htinst/mtinst on a MCall exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE

H

Value written into htinst/mtinst on a SCall exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE

H

Value written into htinst/mtinst on an AccessFault exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which resuls in UNPREDICTABLE

H

Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which resuls in UNPREDICTABLE

H

Value written into htinst/mtinst on a StoreAmoPageFault exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "always transformed standard instruction": Always write a transformed standard instruction as defined by H * "custom": Write a custom value, which resuls in UNPREDICTABLE

H

Value written into htinst/mtinst on a UCall exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE

H

Value written into htinst/mtinst on a VirtualInstruction exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE

H

Value written into htinst/mtinst on a VSCall exception from VU/VS-mode.

Possible values: * "always zero": Always write the value zero * "custom": Write a custom value, which resuls in UNPREDICTABLE

H

Whether or not an EBREAK causes a synchronous exception.

The spec states that implementations may handle EBREAKs transparently without raising a trap, in which case the EEI must provide a builtin.

Sm

Whether or not an ECALL-from-M-mode causes a synchronous exception.

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

Sm

Whether or not an ECALL-from-S-mode causes a synchronous exception.

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

S

Whether or not an ECALL-from-U-mode causes a synchronous exception.

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

U

Whether or not an ECALL-from-VS-mode causes a synchronous exception.

The spec states that implementations may handle ECALLs transparently without raising a trap, in which case the EEI must provide a builtin.

H

When true, writing an illegal value to a WLRL CSR field raises an IllegalInstruction exception.

When false, writing an illegal value to a WLRL CSR field is unpredictable.

Sm

When true, fetching an unimplemented and/or undefined instruction from the standard/reserved encoding space will cause an IllegalInstruction exception.

When false, fetching such an instruction is UNPREDICTABLE.

Sm

For implementations that make satp.MODE read-only zero (always Bare, i.e., no virtual translation is implemented), attempts to execute an SFENCE.VMA instruction might raise an illegal-instruction exception.

TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY indicates whether or not that exception occurs.

TRAP_ON_SFENCE_VMA_WHEN_SATP_MODE_IS_READ_ONLY has no effect when some virtual translation mode is supported.

S

When true, accessing an unimplemented CSR (via a Zicsr instruction) will cause an IllegalInstruction exception.

When false, accessing an unimplemented CSR (via a Zicsr instruction) is unpredictable.

Sm

When true, fetching an unimplemented instruction from the custom encoding space will cause an IllegalInstruction exception.

When false, fetching an unimplemented instruction is UNPREDICTABLE.

Sm

Set of XLENs supported in U-mode. Can be one of:

U

Endianess of data in U-mode. Can be one of:

U

JEDEC Vendor ID bank, for mvendorid

Sm

Vendor JEDEC code offset, for mvendorid

Sm

Number of bits supported in hgatp.VMID (i.e., the supported width of a virtual machine ID).

H

Set of XLENs supported in VS-mode. Can be one of:

H

Endianess of data in VS-mode. Can be one of:

H

Set of XLENs supported in VU-mode. Can be one of:

H

Endianess of data in VU-mode. Can be one of:

H

XLEN in M-mode (AKA MXLEN, tracked by issue #52)

Sm