fclass.s

Single-precision floating-point classify.

This instruction is defined by:

Encoding

Synopsis

The fclass.s instruction examines the value in floating-point register fs1 and writes to integer register rd a 10-bit mask that indicates the class of the floating-point number. The format of the mask is described in the table below. The corresponding bit in rd will be set if the property is true and clear otherwise. All other bits in rd are cleared. Note that exactly one bit in rd will be set. fclass.s does not set the floating-point exception flags.

Table 1. Format of result of `fclass` instruction.
rd bit	Meaning
0	rs1 is \(-\infty\).
1	rs1 is a negative normal number.
2	rs1 is a negative subnormal number.
3	rs1 is \(-0\).
4	rs1 is \(+0\).
5	rs1 is a positive subnormal number.
6	rs1 is a positive normal number.
7	rs1 is \(+\infty\).
8	rs1 is a signaling NaN.
9	rs1 is a quiet NaN.

Access

Always

Decode Variables

Bits<5> fs1 = $encoding[19:15];
Bits<5> rd = $encoding[11:7];

Execution

Pruned, XLEN == 64
Original

check_f_ok($encoding);
Bits<32> sp_value = f[fs1][31:0];
if (is_sp_neg_inf?(sp_value)) {
  X[rd] = 1;
} else if (is_sp_neg_norm?(sp_value)) {
  X[rd] = 2;
} else if (is_sp_neg_subnorm?(sp_value)) {
  X[rd] = 4;
} else if (is_sp_neg_zero?(sp_value)) {
  X[rd] = 8;
} else if (is_sp_pos_zero?(sp_value)) {
  X[rd] = 16;
} else if (is_sp_pos_subnorm?(sp_value)) {
  X[rd] = 32;
} else if (is_sp_pos_norm?(sp_value)) {
  X[rd] = 64;
} else if (is_sp_pos_inf?(sp_value)) {
  X[rd] = 128;
} else if (is_sp_signaling_nan?(sp_value)) {
  X[rd] = 256;
} else {
  assert(is_sp_quiet_nan?(sp_value), "Unexpected SP value");
  X[rd] = 512;
}

check_f_ok($encoding);
Bits<32> sp_value = f[fs1][31:0];
if (is_sp_neg_inf?(sp_value)) {
  X[rd] = 1 << 0;
} else if (is_sp_neg_norm?(sp_value)) {
  X[rd] = 1 << 1;
} else if (is_sp_neg_subnorm?(sp_value)) {
  X[rd] = 1 << 2;
} else if (is_sp_neg_zero?(sp_value)) {
  X[rd] = 1 << 3;
} else if (is_sp_pos_zero?(sp_value)) {
  X[rd] = 1 << 4;
} else if (is_sp_pos_subnorm?(sp_value)) {
  X[rd] = 1 << 5;
} else if (is_sp_pos_norm?(sp_value)) {
  X[rd] = 1 << 6;
} else if (is_sp_pos_inf?(sp_value)) {
  X[rd] = 1 << 7;
} else if (is_sp_signaling_nan?(sp_value)) {
  X[rd] = 1 << 8;
} else {
  assert(is_sp_quiet_nan?(sp_value), "Unexpected SP value");
  X[rd] = 1 << 9;
}

Exceptions

This instruction may result in the following synchronous exceptions:

IllegalInstruction