A Extension
- Implemented Version
-
2.1.0
Synopsis
The atomic-instruction extension, named A, contains instructions that atomically read-modify-write memory to support synchronization between multiple RISC-V harts running in the same memory space. The two forms of atomic instruction provided are load-reserved/store-conditional instructions and atomic fetch-and-op memory instructions. Both types of atomic instruction support various memory consistency orderings including unordered, acquire, release, and sequentially consistent semantics. These instructions allow RISC-V to support the RCsc memory consistency model. cite:[Gharachorloo90memoryconsistency]
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After much debate, the language community and architecture community appear to have finally settled on release consistency as the standard memory consistency model and so the RISC-V atomic support is built around this model. |
Specifying Ordering of Atomic Instructions
The base RISC-V ISA has a relaxed memory model, with the FENCE
instruction used to impose additional ordering constraints. The address
space is divided by the execution environment into memory and I/O
domains, and the FENCE instruction provides options to order accesses to
one or both of these two address domains.
To provide more efficient support for release consistency cite:[Gharachorloo90memoryconsistency], each atomic instruction has two bits, aq and rl, used to specify additional memory ordering constraints as viewed by other RISC-V harts. The bits order accesses to one of the two address domains, memory or I/O, depending on which address domain the atomic instruction is accessing. No ordering constraint is implied to accesses to the other domain, and a FENCE instruction should be used to order across both domains.
If both bits are clear, no additional ordering constraints are imposed on the atomic memory operation. If only the aq bit is set, the atomic memory operation is treated as an acquire access, i.e., no following memory operations on this RISC-V hart can be observed to take place before the acquire memory operation. If only the rl bit is set, the atomic memory operation is treated as a release access, i.e., the release memory operation cannot be observed to take place before any earlier memory operations on this RISC-V hart. If both the aq and rl bits are set, the atomic memory operation is sequentially consistent and cannot be observed to happen before any earlier memory operations or after any later memory operations in the same RISC-V hart and to the same address domain.
Parameters
This extension has the following implementation options:
- LRSC_FAIL_ON_NON_EXACT_LRSC
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Whether or not a Store Conditional fails if its physical address and size do not exactly match the physical address and size of the last Load Reserved in program order (independent of whether or not the SC is in the current reservation set)
- LRSC_FAIL_ON_VA_SYNONYM
- LRSC_MISALIGNED_BEHAVIOR
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What to do when an LR/SC address is misaligned and MISALIGNED_AMO == false.
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'always raise misaligned exception': self-explainitory
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'always raise access fault': self-explainitory
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'custom': Custom behavior; misaligned LR/SC may sometimes raise a misaligned exception and sometimes raise a access fault. Will lead to an 'unpredictable' call on any misaligned LR/SC access
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- LRSC_RESERVATION_STRATEGY
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Strategy used to handle reservation sets.
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"reserve naturally-aligned 64-byte region": Always reserve the 64-byte block containing the LR/SC address
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"reserve naturally-aligned 128-byte region": Always reserve the 128-byte block containing the LR/SC address
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"reserve exactly enough to cover the access": Always reserve exactly the LR/SC access, and no more
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"custom": Custom behavior, leading to an 'unpredictable' call on any LR/SC
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- MISALIGNED_AMO
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whether or not the implementation supports misaligned atomics in main memory
- MUTABLE_MISA_A