sepc
Supervisor Exception Program Counter
Written with the PC of an instruction on an exception or interrupt taken in (H)S-mode.
Also controls where the hart jumps on an exception return from (H)S-mode.
Fields
PC
- Location
-
sepc[63:0] - Description
-
When a trap is taken into S-mode, sepc.PC is written with the virtual address of the instruction that was interrupted or that encountered the exception. Otherwise, sepc.PC is never written by the implementation, though it may be explicitly written by software.
On an exception retun from S-mode (from the SRET instruction), control transfers to the virtual address read out of sepc.PC.
Because PCs are always halfword-aligned, bit 0 of sepc.PC are always read-only 0.
When misa.C is clear, bit 1 is masked to zero. Writes to bit 1 are still captured, and may be visible on the next read with misa.C is set.
Holds bits 63:2 of the virtual address associated with an exception.
- Type
RW-RH |
Read-Write Restricted with Hardware update Field is writeable by software. Only certain values are legal. Writing an illegal value into the field is ignored, such that the field retains its prior state. Hardware also updates the field without an explicit software write.) |
- Reset value
-
UNDEFINED_LEGAL
- Software write
-
This field has special behavior when written by software (e.g., through csrrw).
When software tries to write
csr_value, the field will be written with the return value of the function below.return csr_value.PC & ~64'b1;
Software read
This CSR may return a value that is different from what is stored in hardware.
-
Pruned
-
Original
return CSR[sepc].PC & ~64'b1;if (implemented?(ExtensionName::C) && CSR[misa].C == 1'b1) {
return CSR[sepc].PC & ~64'b1;
} else {
return CSR[sepc].PC;
}