mcycle

Machine Cycle Counter

Counts the number of clock cycles executed by the processor core on which the hart is running. The counter has 64-bit precision on all RV32 and RV64 harts.

The mcycle CSR may be shared between harts on the same core, in which case writes to mcycle will be visible to those harts. The platform should provide a mechanism to indicate which harts share an mcycle CSR.

Attributes

CSR Address

0xb00

Defining extension

  • Zicntr, version >= 0

Length

64-bit

Privilege Mode

M

Format

mcycle format
Figure 1. mcycle format

Field Summary

Name Location Type Reset Value

COUNT

63:0

RW-RH

UNDEFINED_LEGAL

Fields

COUNT

Location

mcycle[63:0]

Description

Cycle counter.

Aliased as cycle.

Increments every cycle unless:

  • mcountinhibit.CY or its alias scountinhibit.CY is set

  • mcyclecfg.MINH is set and the current privilege level is M

  • mcyclecfg.SINH or its alias instretcfg.SINH is set and the current privilege level is (H)S

  • mcyclecfg.UINH or its alias instretcfg.SINH is set and the current privilege level is U

  • mcyclecfg.VSINH or its alias instretcfg.SINH is set and the current privilege level is VS

  • mcyclecfg.VUINH or its alias instretcfg.SINH is set and the current privilege level is VU

Type

RW-RH

Read-Write Restricted with Hardware update

Field is writeable by software. Only certain values are legal. Writing an illegal value into the field is ignored, such that the field retains its prior state. Hardware also updates the field without an explicit software write.)
Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (xlen() == 32) {
  return sw_write_mcycle({read_mcycle()[63:31], csr_value.COUNT[31:0]});
} else {
  return sw_write_mcycle(csr_value.COUNT);
}

Software read

This CSR may return a value that is different from what is stored in hardware.

  • Pruned

  • Original

return read_mcycle();
return read_mcycle();