mtvec

Machine Trap Vector Control

Controls where traps jump.

Attributes

CSR Address

0x305

Defining extension

  • Sm, version >= 0

Length

64-bit

Privilege Mode

M

Format

mtvec format
Figure 1. mtvec format

Field Summary

Name Location Type Reset Value

BASE

63:2

RW-R

0

MODE

1:0

RW-R

UNDEFINED_LEGAL

Fields

BASE

Location

mtvec[63:2]

Description

Bits [MXLEN-1:2] of the exception vector physical address for any trap taken in M-mode.

The implementation physical memory map may resitrict which values are legal in this field.

Type

RW-R

Read-Write Restricted

Field is writable by software. Only certain values are legal. Writing an illegal value into the field is ignored, and the field retains its prior state.

Reset value

0

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

return csr_value.BASE;

MODE

Location

mtvec[1:0]

Description

Vectoring mode for asynchronous interrupts.

0 - Direct, 1 - Vectored

When Direct, all synchronous exceptions and asynchronous interrupts jump to (mtvec.BASE << 2).

When Vectored, asynchronous interrupts jump to (mtvec.BASE << 2 + mcause*4) while synchronous exceptions continue to jump to (mtvec.BASE << 2).

Type

RW-R

Read-Write Restricted

Field is writable by software. Only certain values are legal. Writing an illegal value into the field is ignored, and the field retains its prior state.

Reset value

UNDEFINED_LEGAL

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (csr_value.MODE == 0) {
  return csr_value.MODE;
} else if (csr_value.MODE == 1) {
  return csr_value.MODE;
} else {
  return UNDEFINED_LEGAL_DETERMINISTIC;
}