mip

Machine Interrupt Pending

The mie and mip CSRs are MXLEN-bit read/write registers used when the CLINT or PLIC interrupt controllers are present. Note that the CLINT refers to an interrupt controller used by some RISC-V implementations but isn’t a ratified RISC-V International standard.

The mip CSR contains information on pending interrupts, while mie is the corresponding CSR containing interrupt enable bits. Interrupt cause number i (as reported in the mcause CSR) corresponds to bit i in both mip and mie. Bits 15:0 are allocated to standard interrupt causes only, while bits 16 and above are designated for platform use.

Interrupts designated for platform use may be designated for custom use at the platform’s discretion.

An interrupt i will trap to M-mode (causing the privilege mode to change to M-mode) if all of the following are true:

  • either the current privilege mode is M and the MIE bit in the mstatus register is set, or the current privilege mode has less privilege than M-mode;

  • bit i is set in both mip and mie

  • if register mideleg exists, bit i is not set in mideleg.

These conditions for an interrupt trap to occur must be evaluated in a bounded amount of time from when an interrupt becomes, or ceases to be, pending in mip, and must also be evaluated immediately following the execution of an xRET instruction or an explicit write to a CSR on which these interrupt trap conditions expressly depend (including mip, mie, mstatus, and mideleg).

Interrupts to M-mode take priority over any interrupts to lower privilege modes.

Each individual bit in register mip may be writable or may be read-only. When bit i in mip is writable, a pending interrupt i can be cleared by writing 0 to this bit. If interrupt i can become pending but bit i in mip is read-only, the implementation must provide some other mechanism for clearing the pending interrupt.

A bit in mie must be writable if the corresponding interrupt can ever become pending. Bits of mie that are not writable must be read-only zero.

The machine-level interrupt registers handle a few root interrupt sources which are assigned a fixed service priority for simplicity, while separate external interrupt controllers can implement a more complex prioritization scheme over a much larger set of interrupts that are then muxed into the machine-level interrupt sources.


The non-maskable interrupt is not made visible via the mip register as its presence is implicitly known when executing the NMI trap handler.

If supervisor mode is implemented, bits mip.SEIP and mie.SEIE are the interrupt-pending and interrupt-enable bits for supervisor-level external interrupts. SEIP is writable in mip, and may be written by M-mode software to indicate to S-mode that an external interrupt is pending. Additionally, the platform-level interrupt controller may generate supervisor-level external interrupts. Supervisor-level external interrupts are made pending based on the logical-OR of the software-writable SEIP bit and the signal from the external interrupt controller. When mip is read with a CSR instruction, the value of the SEIP bit returned in the rd destination register is the logical-OR of the software-writable bit and the interrupt signal from the interrupt controller, but the signal from the interrupt controller is not used to calculate the value written to SEIP. Only the software-writable SEIP bit participates in the read-modify-write sequence of a CSRRS or CSRRC instruction.

For example, if we name the software-writable SEIP bit B and the signal from the external interrupt controller E, then if csrrs t0, mip, t1 is executed, t0[9] is written with B || E, then B is written with B || t1[9]. If csrrw t0, mip, t1 is executed, then t0[9] is written with B || E, and B is simply written with t1[9]. In neither case does B depend upon E.

The SEIP field behavior is designed to allow a higher privilege layer to mimic external interrupts cleanly, without losing any real external interrupts. The behavior of the CSR instructions is slightly modified from regular CSR accesses as a result.

If supervisor mode is implemented, bits mip.STIP and mie.STIE are the interrupt-pending and interrupt-enable bits for supervisor-level timer interrupts. STIP is writable in mip, and may be written by M-mode software to deliver timer interrupts to S-mode.

If supervisor mode is implemented, bits mip.SSIP and mie.SSIE are the interrupt-pending and interrupt-enable bits for supervisor-level software interrupts. SSIP is writable in mip and may also be set to 1 by a platform-specific interrupt controller.

bits mip.LCOFIP and mie.LCOFIE are the interrupt-pending and interrupt-enable bits for local counter-overflow interrupts. LCOFIP is read-write in mip and reflects the occurrence of a local counter-overflow overflow interrupt request resulting from any of the mhpmeventn.OF bits being set.

Multiple simultaneous interrupts destined for M-mode are handled in the following decreasing priority order: MEI, MSI, MTI, SEI, SSI, STI, LCOFI.

The machine-level interrupt fixed-priority ordering rules were developed with the following rationale.

Interrupts for higher privilege modes must be serviced before interrupts for lower privilege modes to support preemption.

The platform-specific machine-level interrupt sources in bits 16 and above have platform-specific priority, but are typically chosen to have the highest service priority to support very fast local vectored interrupts.

External interrupts are handled before internal (timer/software) interrupts as external interrupts are usually generated by devices that might require low interrupt service times.

Software interrupts are handled before internal timer interrupts, because internal timer interrupts are usually intended for time slicing, where time precision is less important, whereas software interrupts are used for inter-processor messaging. Software interrupts can be avoided when high-precision timing is required, or high-precision timer interrupts can be routed via a different interrupt path. Software interrupts are located in the lowest four bits of mip as these are often written by software, and this position allows the use of a single CSR instruction with a five-bit immediate.

Restricted views of the mip and mie registers appear as the sip and sie registers for supervisor level. If an interrupt is delegated to S-mode by setting a bit in the mideleg register, it becomes visible in the sip register and is maskable using the sie register. Otherwise, the corresponding bits in sip and sie are read-only zero.

Attributes

CSR Address

0x344

Defining extension

  • Sm, version >= 0

Length

64-bit

Privilege Mode

M

Format

mip format
Figure 1. mip format

Field Summary

Name Location Type Reset Value

SSIP

1

RW

0

VSSIP

2

RW

0

MSIP

3

RO

0

STIP

5

RW

0

VSTIP

6

RO-H

0

MTIP

7

RO-H

0

SEIP

9

RW-H

0

VSEIP

10

RO-H

0

MEIP

11

RO-H

0

SGEIP

12

RO-H

0

LCOFIP

13

RW-H

0

Fields

SSIP

Location

mip[1]

Description

Supervisor Software Interrupt Pending

Reports the current pending state of an (H)S-mode software interrupt, which is generated by writing to this field.

When using AIA/IMSIC, IPIs are expected to be delivered as external interrupts and SSIP is not backed by any hardware update (aside from any aliasing effects). However, SSIP is still writable by M-mode software and, when written, can be used to generate an S-mode Software Interrupt.

Aliases:

Type

RW

Read-Write

Field is writable by software. Any value that fits in the field is acceptable and shall be retained for subsequent reads.

Reset value

0

VSSIP

Location

mip[2]

Description

Virtual Supervisor Software Interrupt Pending

Reports the current pending state of a VS-mode software interrupt, which is generated by writing to this field.

When using AIA/IMSIC, IPIs are expected to be delivered as external interrupts and VSSIP is not backed by any hardware update (aside from any aliased writes). However, VSSIP is still writable by M-mode software and, when written, can be used to generate a VS-mode Software Interrupt.

Aliases:

  • hip.VSSIP

  • hvip.VSSIP

  • vsip.SSIP when hideleg.VSSI is set

Type

RW

Read-Write

Field is writable by software. Any value that fits in the field is acceptable and shall be retained for subsequent reads.

Reset value

0

MSIP

Location

mip[3]

Description

Machine Software Interrupt Pending

Unused field.

With AIA/IMSIC, IPIs are delievered as external interrupts. As a result, this bit is unused and hardwired to 0.

Type

RO

Read-Only

Field has a hardwired value that does not change. Writes to an RO field are ignored.

Reset value

0

STIP

Location

mip[5]

Description

Supervisor Timer Interrupt Pending

Reports the current pending state of an (H)S-mode timer interrupt , which is normally controlled by the stimecmp CSR.

When menvcfg.STCE is set, mip.STIP is RO-H, and is completely controlled by the timer interrupt device (using stimecmp).

When menvcfg.STCE is clear, mip.STIP is RW, and M-mode software may write the bit to inject a Supervisor Timer Interrupt.

Aliases:

Type

RW

Read-Write

Field is writable by software. Any value that fits in the field is acceptable and shall be retained for subsequent reads.

Reset value

0

VSTIP

Location

mip[6]

Description

Virtual Supervisor Timer Interrupt Pending

Reports the current pending state of a VS-mode timer interrupt , which is normally controlled by the vstimecmp CSR, but can also be injected by the hypervisor through hvip.VSTIP.

When menvcfg.STCE is set (enabling the Sstc extension), mip.VSTIP is the logical OR of hvip.VSTIP and the VS-level interrupt signal generated by the timer device (controlled by the value of vstimecmp).

When menvcfg.STCE is clear (disabling the Sstc extension), mip.VSTIP is exactly the value of hvip.VSTIP.

mip.VSTIP is never writable. If VS-mode software wants to clear the bit, it must do so by writing the vstimecmp register or by calling into the hypervisor (which can then clear hvip.VSTIP).

Aliases:

  • hip.VSTIP

  • vsip.STIP when hideleg.VSTI is set

  • hvip.VSTIP when menvcfg.STCE is clear (though hvip.VSTIP is writeable)

Type

RO-H

Read-Only with Hardware update

Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value

0

MTIP

Location

mip[7]

Description

Machine Timer Interrupt Pending

Reports the current pending state of an M-mode timer interrupt.

Bit is controlled by the timer device (using mtimecmp), and is not writeable.

Type

RO-H

Read-Only with Hardware update

Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value

0

SEIP

Location

mip[9]

Description

Supervisor External Interrupt Pending

Reports the current pending state of an (H)S-mode external interrupt.

This field has two parts: a software-writeable shadow value and a wire from the interrupt controller. The value presented to software in the bit on a CSR read is the logical OR of the software-writeable value and the interrupt controller value. When software writes this bit, only the shadow value is updated (the interrupt controller is not notified of the write).

The software-writeable shadow value is aliased in mvip.SEIP (Smaia extension).

Alias:

Type

RW-H

Read-Write with Hardware update

Field is writable by software. Any value that fits in the field is acceptable. Hardware also updates the field without an explicit software write.

Reset value

0

VSEIP

Location

mip[10]

Description

Virtual Supervisor External Interrupt Pending

Reports the current pending state of a VS-mode external interrupt.

This field is the logical OR of hvip.VSEIP and the wire coming from the interrupt controller.

The field is not writable by software (i.e., unlike the behavior of mip.SEIP/mvip.SEIP, attempted writes to mip.VSEIP do not propagate to hvip.VSEIP) .

Aliases:

  • hip.VSEIP

  • vsip.SEIP when hideleg.VSEI is set

Type

RO-H

Read-Only with Hardware update

Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value

0

MEIP

Location

mip[11]

Description

Machine External Interrupt Pending

Reports the current pending state of an M-mode external interrupt.

MEIP is controlled by the external interrupt controller (AIA) . It is not writable by software.

Type

RO-H

Read-Only with Hardware update

Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value

0

SGEIP

Location

mip[12]

Description

Supervisor Guest External Interrupt Pending

Read-only summary of any pending Supervisor Guest External Interrupt Pending, i.e.: the logical-OR reduction of the hgeip register.

Alias:

  • hip.SGEIP

Type

RO-H

Read-Only with Hardware update

Writes are ignored. Reads reflect a value dynamically generated by hardware.

Reset value

0

LCOFIP

Location

mip[13]

Description

Local Counter Overflow Interrupt pending

When hideleg.LCOFI is set, vsip.LCOFIP, sip.LCOFIP, and mip.LCOFIP are all aliases.

When a counter overflow interrupt occurs, a hidden sticky bit is set.

Software writes 0 to mip.LCOFIP to clear the pending interrupt.

Aliases:

Type

RW-H

Read-Write with Hardware update

Field is writable by software. Any value that fits in the field is acceptable. Hardware also updates the field without an explicit software write.

Reset value

0