vstvec

Supervisor Trap Vector

Controls where traps jump.

Attributes

CSR Address

0x205

Defining extension

Length

64-bit

Privilege Mode

Figure 1. vstvec format

Name Location Type Reset Value

Name	Location	Type	Reset Value
`BASE`	63:2	RW-R	0
`MODE`	1:0	RW-R	0

63:2

RW-R

1:0

RW-R

Location: vstvec[63:2]
Description: Bit 63:0 of the virtual address of the exception vector for any trap taken into VS-mode.

If the base address is written with a non-cannonical address (i.e., bits 63:49 do not match bit 48), the write should be ignored.
Type

RW-R	Read-Write Restricted Field is writable by software. Only certain values are legal. Writing an illegal value into the field is ignored, and the field retains its prior state.

Reset value

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

return csr_value.BASE;

Location: vstvec[1:0]
Description: Vectoring mode for asynchronous interrupts taken into VS-mode.

0 - Direct, 1 - Vectored

When Direct, all synchronous exceptions and asynchronous interrupts jump to (vstvec.BASE << 2).

When Vectored, asynchronous interrupts jump to (vstvec.BASE << 2 + vscause*4) while synchronous exceptions continue to jump to (vstvec.BASE << 2).
Type

RW-R	Read-Write Restricted Field is writable by software. Only certain values are legal. Writing an illegal value into the field is ignored, and the field retains its prior state.

Reset value

Software write

This field has special behavior when written by software (e.g., through csrrw).

When software tries to write csr_value, the field will be written with the return value of the function below.

if (csr_value.MODE == 0 || csr_value.MODE == 1) {
  return csr_value.MODE;
} else {
  return UNDEFINED_LEGAL_DETERMINISTIC;
}