stvec
Supervisor Trap Vector
Controls where traps jump.
Fields
BASE
- Location
-
stvec[63:2]
- Description
-
Bit 63:0 of the virtual address of the exception vector for any trap taken into S-mode.
If the base address is written with a non-cannonical address (i.e., bits 63:49 do not match bit 48), the write should be ignored.
- Type
RW-R |
Read-Write Restricted Field is writable by software. Only certain values are legal. Writing an illegal value into the field is ignored, and the field retains its prior state. |
- Reset value
-
UNDEFINED_LEGAL
- Software write
-
This field has special behavior when written by software (e.g., through csrrw).
When software tries to write
csr_value
, the field will be written with the return value of the function below.return csr_value.BASE;
MODE
- Location
-
stvec[1:0]
- Description
-
Vectoring mode for asynchronous interrupts.
0 - Direct, 1 - Vectored
When Direct, all synchronous exceptions and asynchronous interrupts jump to (stvec.BASE << 2).
When Vectored, asynchronous interrupts jump to (stvec.BASE << 2 + scause*4) while synchronous exceptions continue to jump to (stvec.BASE << 2).
- Type
RW-R |
Read-Write Restricted Field is writable by software. Only certain values are legal. Writing an illegal value into the field is ignored, and the field retains its prior state. |
- Reset value
-
0
- Software write
-
This field has special behavior when written by software (e.g., through csrrw).
When software tries to write
csr_value
, the field will be written with the return value of the function below.if (STVEC_MODE_DIRECT && csr_value.MODE == 0) { return 0; } else if (STVEC_MODE_VECTORED && csr_value.MODE == 1) { return 1; } else { return UNDEFINED_LEGAL_DETERMINISTIC; }